Device Tree changes for Ux500 and ARM SOC:

- Document Snoop Control Unit (SCU) bindings
 - Document Ux500 board bindings
 - Define the backup RAM in the DBx500 device tree
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVbEwwAAoJEEEQszewGV1zw5IQAMgEalCaSArXm/a12eogltuE
 rGzJtP6MRwqLA4dGe+rOnUEsw2+jX1uBpUsBt7akBRbl2prRUpm89SJxZg8E5YpG
 u2c+ODrh1lp4sRpAtKiMrLVx+hIjR4YFEa2cW0/OAJKG+4h1RXeQlXW3bw9q0qov
 dO+M+NlcmWHyaJU9bNHYPZNYtG+9rVYY8kEK/LFe1xiY/VYC8KIe+gikR/R9WHI1
 PZgAi1rARLeKAC7eThUDA+XnhzpxwYyqsxHsLV92l0l/cfly6DKCmZ1Zn9jk7v4b
 L24jZ8OpHhJX5s//vsBmLxSobisuL8aLJDHCkrBmIb+geRsphOYmYTwmKdRJ2YkB
 CyuxmvjdpKNiBIb8SGEKplrRaAexRfjXxX1GdNZNzdvIDo7T1hrM3/Fzo5TXxP61
 Tgtu3I2Cwa3luDxFKaGlgldihvhUVPcAoBQUXyF57teWIh4iwTcrGZ3Li9kxTY32
 ZvunTP/z8XjWRKFHv5KFCnnpxoQLDB/aHuv36H94hol5Nf95MC0EjGvBRM582z+u
 1znExgtfSUt0BfqaxFgTieIu8RrQK0bxGcwBK6Okmv+j2BjTnE10ZuoqZSCaurOQ
 QEkO336JNyYSwSu9Bxcwcx5x/qB+X5yuZLvmzhOp8Ld0omUngOqSpBtxdQQNQBK5
 9qwI0QJ0Unc3rSgkJ6Ho
 =IRmr
 -----END PGP SIGNATURE-----

Merge tag 'dt-for-armsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt

Merge "Device Tree changes for Ux500 and ARM SOC" from Linus Walleij:

- Document Snoop Control Unit (SCU) bindings
- Document Ux500 board bindings
- Define the backup RAM in the DBx500 device tree

* tag 'dt-for-armsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
  ARM: ux500: define the backupram in the device tree
  ARM: ux500: add board documentation
  ARM: scu: document Snoop Control Unit DT bindings

Documentation/devicetree/bindings/arm/scu.txt

@@ -0,0 +1,25 @@
+* ARM Snoop Control Unit (SCU)
+
+As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
+with a Snoop Control Unit. The register range is usually 256 (0x100)
+bytes.
+
+References:
+
+- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
+  Revision r2p0
+- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
+  Revision r0p1
+
+- compatible : Should be:
+	"arm,cortex-a9-scu"
+	"arm,cortex-a5-scu"
+
+- reg : Specify the base address and the size of the SCU register window.
+
+Example:
+
+scu@a04100000 {
+	compatible = "arm,cortex-a9-scu";
+	reg = <0xa0410000 0x100>;
+};

Documentation/devicetree/bindings/arm/ux500/boards.txt

@@ -0,0 +1,83 @@
+ST-Ericsson Ux500 boards
+------------------------
+
+Required properties (in root node) one of these:
+	compatible = "st-ericsson,mop500" (legacy)
+	compatible = "st-ericsson,u8500"
+
+Required node (under root node):
+
+soc: represents the system-on-chip and contains the chip
+peripherals
+
+Required property of soc node, one of these:
+	compatible = "stericsson,db8500"
+
+Required subnodes under soc node:
+
+backupram: (used for CPU spin tables and for storing data
+during retention, system won't boot without this):
+	compatible = "ste,dbx500-backupram"
+
+scu:
+	see binding for arm/scu.txt
+
+interrupt-controller:
+	see binding for arm/gic.txt
+
+timer:
+	see binding for arm/twd.txt
+
+clocks:
+	see binding for clocks/ux500.txt
+
+Example:
+
+/dts-v1/;
+
+/ {
+        model = "ST-Ericsson HREF (pre-v60) and ST UIB";
+        compatible = "st-ericsson,mop500", "st-ericsson,u8500";
+
+        soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "stericsson,db8500";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		backupram@80150000 {
+			compatible = "ste,dbx500-backupram";
+			reg = <0x80150000 0x2000>;
+		};
+
+		intc: interrupt-controller@a0411000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			interrupt-controller;
+			reg = <0xa0411000 0x1000>,
+			      <0xa0410100 0x100>;
+		};
+
+		scu@a04100000 {
+			compatible = "arm,cortex-a9-scu";
+			reg = <0xa0410000 0x100>;
+		};
+
+		timer@a0410600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xa0410600 0x20>;
+			interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
+			clocks = <&smp_twd_clk>;
+		};
+
+		clocks {
+			compatible = "stericsson,u8500-clks";
+
+			smp_twd_clk: smp-twd-clock {
+				#clock-cells = <0>;
+			};
+		};
+        };
+};

arch/arm/boot/dts/ste-dbx5x0.dtsi

@@ -190,6 +190,15 @@
 			reg = <0xa0410000 0x100>;
 		};
 
+		/*
+		 * The backup RAM is used for retention during sleep
+		 * and various things like spin tables
+		 */
+		backupram@80150000 {
+			compatible = "ste,dbx500-backupram";
+			reg = <0x80150000 0x2000>;
+		};
+
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
 			reg = <0xa0412000 0x1000>;