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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
This commit is contained in:
Linus Torvalds
commit
e89227889c
@ -1600,11 +1600,11 @@ sys_clone: flushw
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ba,pt %xcc, sparc_do_fork
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add %sp, PTREGS_OFF, %o2
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ret_from_syscall:
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/* Clear SPARC_FLAG_NEWCHILD, switch_to leaves thread.flags in
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* %o7 for us. Check performance counter stuff too.
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/* Clear current_thread_info()->new_child, and
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* check performance counter stuff too.
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*/
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andn %o7, _TIF_NEWCHILD, %l0
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stx %l0, [%g6 + TI_FLAGS]
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stb %g0, [%g6 + TI_NEW_CHILD]
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ldx [%g6 + TI_FLAGS], %l0
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call schedule_tail
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mov %g7, %o0
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andcc %l0, _TIF_PERFCTR, %g0
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@ -1720,12 +1720,11 @@ ret_sys_call:
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/* Check if force_successful_syscall_return()
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* was invoked.
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*/
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ldx [%curptr + TI_FLAGS], %l0
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andcc %l0, _TIF_SYSCALL_SUCCESS, %g0
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be,pt %icc, 1f
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andn %l0, _TIF_SYSCALL_SUCCESS, %l0
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ldub [%curptr + TI_SYS_NOERROR], %l0
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brz,pt %l0, 1f
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nop
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ba,pt %xcc, 80f
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stx %l0, [%curptr + TI_FLAGS]
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stb %g0, [%curptr + TI_SYS_NOERROR]
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1:
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cmp %o0, -ERESTART_RESTARTBLOCK
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@ -782,8 +782,14 @@ static void distribute_irqs(void)
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}
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#endif
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struct sun5_timer {
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u64 count0;
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u64 limit0;
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u64 count1;
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u64 limit1;
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};
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struct sun5_timer *prom_timers;
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static struct sun5_timer *prom_timers;
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static u64 prom_limit0, prom_limit1;
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static void map_prom_timers(void)
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@ -839,18 +845,6 @@ static void kill_prom_timer(void)
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: "g1", "g2");
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}
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void enable_prom_timer(void)
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{
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if (!prom_timers)
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return;
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/* Set it to whatever was there before. */
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prom_timers->limit1 = prom_limit1;
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prom_timers->count1 = 0;
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prom_timers->limit0 = prom_limit0;
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prom_timers->count0 = 0;
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}
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void init_irqwork_curcpu(void)
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{
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register struct irq_work_struct *workp asm("o2");
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@ -621,8 +621,8 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
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memcpy(child_trap_frame, (((struct sparc_stackf *)regs)-1), (TRACEREG_SZ+STACKFRAME_SZ));
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t->flags = (t->flags & ~((0xffUL << TI_FLAG_CWP_SHIFT) | (0xffUL << TI_FLAG_CURRENT_DS_SHIFT))) |
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_TIF_NEWCHILD |
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(((regs->tstate + 1) & TSTATE_CWP) << TI_FLAG_CWP_SHIFT);
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t->new_child = 1;
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t->ksp = ((unsigned long) child_trap_frame) - STACK_BIAS;
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t->kregs = (struct pt_regs *)(child_trap_frame+sizeof(struct sparc_stackf));
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t->fpsaved[0] = 0;
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@ -137,7 +137,7 @@ void __init smp_callin(void)
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/* Clear this or we will die instantly when we
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* schedule back to this idler...
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*/
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clear_thread_flag(TIF_NEWCHILD);
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current_thread_info()->new_child = 0;
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/* Attach to the address space of init_task. */
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atomic_inc(&init_mm.mm_count);
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@ -2125,6 +2125,8 @@ void __init trap_init(void)
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TI_PCR != offsetof(struct thread_info, pcr_reg) ||
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TI_CEE_STUFF != offsetof(struct thread_info, cee_stuff) ||
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TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
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TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
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TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
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TI_FPREGS != offsetof(struct thread_info, fpregs) ||
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(TI_FPREGS & (64 - 1)))
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thread_info_offsets_are_bolixed_dave();
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@ -71,20 +71,6 @@ config SUN_JSFLASH
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# XXX Why don't we do "source drivers/char/Config.in" somewhere?
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# no shit
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config APM_RTC_IS_GMT
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bool
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depends on EXPERIMENTAL && SPARC32 && PCI
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default y
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help
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Say Y here if your RTC (Real Time Clock a.k.a. hardware clock)
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stores the time in GMT (Greenwich Mean Time). Say N if your RTC
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stores localtime.
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It is in fact recommended to store GMT in your RTC, because then you
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don't have to worry about daylight savings time changes. The only
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reason not to use GMT in your RTC is if you also run a broken OS
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that doesn't understand GMT.
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config RTC
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tristate "PC-style Real Time Clock Support"
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depends on PCI && EXPERIMENTAL && SPARC32
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@ -1515,8 +1515,7 @@ static void aurora_close(struct tty_struct * tty, struct file * filp)
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*/
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timeout = jiffies+HZ;
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while(port->SRER & SRER_TXEMPTY) {
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current->state = TASK_INTERRUPTIBLE;
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schedule_timeout(port->timeout);
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msleep_interruptible(jiffies_to_msecs(port->timeout));
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if (time_after(jiffies, timeout))
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break;
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}
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@ -1533,8 +1532,7 @@ static void aurora_close(struct tty_struct * tty, struct file * filp)
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port->tty = 0;
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if (port->blocked_open) {
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if (port->close_delay) {
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current->state = TASK_INTERRUPTIBLE;
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schedule_timeout(port->close_delay);
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msleep_interruptible(jiffies_to_msecs(port->close_delay));
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}
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wake_up_interruptible(&port->open_wait);
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}
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@ -4,13 +4,14 @@
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* Copyright (C) 2001 David S. Miller (davem@redhat.com)
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*/
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#define __KERNEL_SYSCALLS__
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <asm/oplib.h>
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#include <asm/ebus.h>
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#define __KERNEL_SYSCALLS__
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static int errno;
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#include <asm/unistd.h>
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@ -19,6 +19,8 @@
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* Daniele Bellucci <bellucda@tiscali.it>
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*/
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#define __KERNEL_SYSCALLS__
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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@ -35,7 +37,6 @@
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#include <asm/uaccess.h>
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#include <asm/envctrl.h>
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#define __KERNEL_SYSCALLS__
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static int errno;
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#include <asm/unistd.h>
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@ -1007,7 +1008,7 @@ static int kenvctrld(void *__unused)
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return -ENODEV;
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}
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poll_interval = 5 * HZ; /* TODO env_mon_interval */
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poll_interval = 5000; /* TODO env_mon_interval */
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daemonize("kenvctrld");
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allow_signal(SIGKILL);
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@ -1016,10 +1017,7 @@ static int kenvctrld(void *__unused)
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printk(KERN_INFO "envctrl: %s starting...\n", current->comm);
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for (;;) {
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current->state = TASK_INTERRUPTIBLE;
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schedule_timeout(poll_interval);
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if(signal_pending(current))
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if(msleep_interruptible(poll_interval))
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break;
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for (whichcpu = 0; whichcpu < ENVCTRL_MAX_CPU; ++whichcpu) {
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@ -88,14 +88,16 @@ void vfc_i2c_delay_wakeup(struct vfc_dev *dev)
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void vfc_i2c_delay_no_busy(struct vfc_dev *dev, unsigned long usecs)
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{
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DEFINE_WAIT(wait);
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init_timer(&dev->poll_timer);
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dev->poll_timer.expires = jiffies +
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((unsigned long)usecs*(HZ))/1000000;
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dev->poll_timer.expires = jiffies + usecs_to_jiffies(usecs);
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dev->poll_timer.data=(unsigned long)dev;
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dev->poll_timer.function=(void *)(unsigned long)vfc_i2c_delay_wakeup;
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add_timer(&dev->poll_timer);
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sleep_on(&dev->poll_wait);
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prepare_to_wait(&dev->poll_wait, &wait, TASK_UNINTERRUPTIBLE);
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schedule();
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del_timer(&dev->poll_timer);
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finish_wait(&dev->poll_wait, &wait);
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}
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void inline vfc_i2c_delay(struct vfc_dev *dev)
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@ -20,52 +20,52 @@ extern void change_bit(unsigned long nr, volatile unsigned long *addr);
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/* "non-atomic" versions... */
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static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
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static inline void __set_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *m = addr + (nr >> 6);
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unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
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*m |= (1UL << (nr & 63));
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}
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static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
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static inline void __clear_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *m = addr + (nr >> 6);
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unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
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*m &= ~(1UL << (nr & 63));
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}
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static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
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static inline void __change_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *m = addr + (nr >> 6);
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unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
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*m ^= (1UL << (nr & 63));
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}
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static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
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static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *m = addr + (nr >> 6);
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long old = *m;
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long mask = (1UL << (nr & 63));
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unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
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unsigned long old = *m;
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unsigned long mask = (1UL << (nr & 63));
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|
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*m = (old | mask);
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return ((old & mask) != 0);
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}
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|
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static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
|
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volatile unsigned long *m = addr + (nr >> 6);
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long old = *m;
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long mask = (1UL << (nr & 63));
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unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
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unsigned long old = *m;
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unsigned long mask = (1UL << (nr & 63));
|
||||
|
||||
*m = (old & ~mask);
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return ((old & mask) != 0);
|
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}
|
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|
||||
static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr)
|
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static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
|
||||
{
|
||||
volatile unsigned long *m = addr + (nr >> 6);
|
||||
long old = *m;
|
||||
long mask = (1UL << (nr & 63));
|
||||
unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
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unsigned long old = *m;
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unsigned long mask = (1UL << (nr & 63));
|
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|
||||
*m = (old ^ mask);
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return ((old & mask) != 0);
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@ -79,13 +79,13 @@ static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr
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||||
#define smp_mb__after_clear_bit() barrier()
|
||||
#endif
|
||||
|
||||
static __inline__ int test_bit(int nr, __const__ volatile unsigned long *addr)
|
||||
static inline int test_bit(int nr, __const__ volatile unsigned long *addr)
|
||||
{
|
||||
return (1UL & ((addr)[nr >> 6] >> (nr & 63))) != 0UL;
|
||||
return (1UL & (addr[nr >> 6] >> (nr & 63))) != 0UL;
|
||||
}
|
||||
|
||||
/* The easy/cheese version for now. */
|
||||
static __inline__ unsigned long ffz(unsigned long word)
|
||||
static inline unsigned long ffz(unsigned long word)
|
||||
{
|
||||
unsigned long result;
|
||||
|
||||
@ -103,7 +103,7 @@ static __inline__ unsigned long ffz(unsigned long word)
|
||||
*
|
||||
* Undefined if no bit exists, so code should check against 0 first.
|
||||
*/
|
||||
static __inline__ unsigned long __ffs(unsigned long word)
|
||||
static inline unsigned long __ffs(unsigned long word)
|
||||
{
|
||||
unsigned long result = 0;
|
||||
|
||||
@ -144,7 +144,7 @@ static inline int sched_find_first_bit(unsigned long *b)
|
||||
* the libc and compiler builtin ffs routines, therefore
|
||||
* differs in spirit from the above ffz (man ffs).
|
||||
*/
|
||||
static __inline__ int ffs(int x)
|
||||
static inline int ffs(int x)
|
||||
{
|
||||
if (!x)
|
||||
return 0;
|
||||
@ -158,7 +158,7 @@ static __inline__ int ffs(int x)
|
||||
|
||||
#ifdef ULTRA_HAS_POPULATION_COUNT
|
||||
|
||||
static __inline__ unsigned int hweight64(unsigned long w)
|
||||
static inline unsigned int hweight64(unsigned long w)
|
||||
{
|
||||
unsigned int res;
|
||||
|
||||
@ -166,7 +166,7 @@ static __inline__ unsigned int hweight64(unsigned long w)
|
||||
return res;
|
||||
}
|
||||
|
||||
static __inline__ unsigned int hweight32(unsigned int w)
|
||||
static inline unsigned int hweight32(unsigned int w)
|
||||
{
|
||||
unsigned int res;
|
||||
|
||||
@ -174,7 +174,7 @@ static __inline__ unsigned int hweight32(unsigned int w)
|
||||
return res;
|
||||
}
|
||||
|
||||
static __inline__ unsigned int hweight16(unsigned int w)
|
||||
static inline unsigned int hweight16(unsigned int w)
|
||||
{
|
||||
unsigned int res;
|
||||
|
||||
@ -182,7 +182,7 @@ static __inline__ unsigned int hweight16(unsigned int w)
|
||||
return res;
|
||||
}
|
||||
|
||||
static __inline__ unsigned int hweight8(unsigned int w)
|
||||
static inline unsigned int hweight8(unsigned int w)
|
||||
{
|
||||
unsigned int res;
|
||||
|
||||
@ -236,7 +236,7 @@ extern unsigned long find_next_zero_bit(const unsigned long *,
|
||||
#define test_and_clear_le_bit(nr,addr) \
|
||||
test_and_clear_bit((nr) ^ 0x38, (addr))
|
||||
|
||||
static __inline__ int test_le_bit(int nr, __const__ unsigned long * addr)
|
||||
static inline int test_le_bit(int nr, __const__ unsigned long * addr)
|
||||
{
|
||||
int mask;
|
||||
__const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
|
||||
|
||||
@ -94,8 +94,9 @@ struct sparc_trapf {
|
||||
#define STACKFRAME32_SZ sizeof(struct sparc_stackf32)
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#define force_successful_syscall_return() \
|
||||
set_thread_flag(TIF_SYSCALL_SUCCESS)
|
||||
#define force_successful_syscall_return() \
|
||||
do { current_thread_info()->syscall_noerror = 1; \
|
||||
} while (0)
|
||||
#define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV))
|
||||
#define instruction_pointer(regs) ((regs)->tpc)
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
@ -46,54 +46,14 @@ extern void __up_read(struct rw_semaphore *sem);
|
||||
extern void __up_write(struct rw_semaphore *sem);
|
||||
extern void __downgrade_write(struct rw_semaphore *sem);
|
||||
|
||||
static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
|
||||
static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
|
||||
{
|
||||
int tmp = delta;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1:\tlduw [%2], %%g1\n\t"
|
||||
"add %%g1, %1, %%g7\n\t"
|
||||
"cas [%2], %%g1, %%g7\n\t"
|
||||
"cmp %%g1, %%g7\n\t"
|
||||
"membar #StoreLoad | #StoreStore\n\t"
|
||||
"bne,pn %%icc, 1b\n\t"
|
||||
" nop\n\t"
|
||||
"mov %%g7, %0\n\t"
|
||||
: "=&r" (tmp)
|
||||
: "0" (tmp), "r" (sem)
|
||||
: "g1", "g7", "memory", "cc");
|
||||
|
||||
return tmp + delta;
|
||||
return atomic_add_return(delta, (atomic_t *)(&sem->count));
|
||||
}
|
||||
|
||||
#define rwsem_atomic_add rwsem_atomic_update
|
||||
|
||||
static __inline__ __u16 rwsem_cmpxchgw(struct rw_semaphore *sem, __u16 __old, __u16 __new)
|
||||
static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
|
||||
{
|
||||
u32 old = (sem->count & 0xffff0000) | (u32) __old;
|
||||
u32 new = (old & 0xffff0000) | (u32) __new;
|
||||
u32 prev;
|
||||
|
||||
again:
|
||||
__asm__ __volatile__("cas [%2], %3, %0\n\t"
|
||||
"membar #StoreLoad | #StoreStore"
|
||||
: "=&r" (prev)
|
||||
: "0" (new), "r" (sem), "r" (old)
|
||||
: "memory");
|
||||
|
||||
/* To give the same semantics as x86 cmpxchgw, keep trying
|
||||
* if only the upper 16-bits changed.
|
||||
*/
|
||||
if (prev != old &&
|
||||
((prev & 0xffff) == (old & 0xffff)))
|
||||
goto again;
|
||||
|
||||
return prev & 0xffff;
|
||||
}
|
||||
|
||||
static __inline__ signed long rwsem_cmpxchg(struct rw_semaphore *sem, signed long old, signed long new)
|
||||
{
|
||||
return cmpxchg(&sem->count,old,new);
|
||||
atomic_add(delta, (atomic_t *)(&sem->count));
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
@ -56,52 +56,6 @@ extern void cheetah_enable_pcache(void);
|
||||
SPITFIRE_HIGHEST_LOCKED_TLBENT : \
|
||||
CHEETAH_HIGHEST_LOCKED_TLBENT)
|
||||
|
||||
static __inline__ unsigned long spitfire_get_isfsr(void)
|
||||
{
|
||||
unsigned long ret;
|
||||
|
||||
__asm__ __volatile__("ldxa [%1] %2, %0"
|
||||
: "=r" (ret)
|
||||
: "r" (TLB_SFSR), "i" (ASI_IMMU));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static __inline__ unsigned long spitfire_get_dsfsr(void)
|
||||
{
|
||||
unsigned long ret;
|
||||
|
||||
__asm__ __volatile__("ldxa [%1] %2, %0"
|
||||
: "=r" (ret)
|
||||
: "r" (TLB_SFSR), "i" (ASI_DMMU));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static __inline__ unsigned long spitfire_get_sfar(void)
|
||||
{
|
||||
unsigned long ret;
|
||||
|
||||
__asm__ __volatile__("ldxa [%1] %2, %0"
|
||||
: "=r" (ret)
|
||||
: "r" (DMMU_SFAR), "i" (ASI_DMMU));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_put_isfsr(unsigned long sfsr)
|
||||
{
|
||||
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
|
||||
"membar #Sync"
|
||||
: /* no outputs */
|
||||
: "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_put_dsfsr(unsigned long sfsr)
|
||||
{
|
||||
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
|
||||
"membar #Sync"
|
||||
: /* no outputs */
|
||||
: "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU));
|
||||
}
|
||||
|
||||
/* The data cache is write through, so this just invalidates the
|
||||
* specified line.
|
||||
*/
|
||||
@ -193,90 +147,6 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
|
||||
"i" (ASI_ITLB_DATA_ACCESS));
|
||||
}
|
||||
|
||||
/* Spitfire hardware assisted TLB flushes. */
|
||||
|
||||
/* Context level flushes. */
|
||||
static __inline__ void spitfire_flush_dtlb_primary_context(void)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (0x40), "i" (ASI_DMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_itlb_primary_context(void)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (0x40), "i" (ASI_IMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_dtlb_secondary_context(void)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (0x50), "i" (ASI_DMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_itlb_secondary_context(void)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (0x50), "i" (ASI_IMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_dtlb_nucleus_context(void)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (0x60), "i" (ASI_DMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_itlb_nucleus_context(void)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (0x60), "i" (ASI_IMMU_DEMAP));
|
||||
}
|
||||
|
||||
/* Page level flushes. */
|
||||
static __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (page), "i" (ASI_DMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_itlb_primary_page(unsigned long page)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (page), "i" (ASI_IMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (page | 0x10), "i" (ASI_DMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
"membar #Sync"
|
||||
: /* No outputs */
|
||||
: "r" (page | 0x10), "i" (ASI_IMMU_DEMAP));
|
||||
}
|
||||
|
||||
static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
|
||||
{
|
||||
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
||||
|
||||
@ -190,24 +190,23 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \
|
||||
"wrpr %%g1, %%cwp\n\t" \
|
||||
"ldx [%%g6 + %3], %%o6\n\t" \
|
||||
"ldub [%%g6 + %2], %%o5\n\t" \
|
||||
"ldx [%%g6 + %4], %%o7\n\t" \
|
||||
"ldub [%%g6 + %4], %%o7\n\t" \
|
||||
"mov %%g6, %%l2\n\t" \
|
||||
"wrpr %%o5, 0x0, %%wstate\n\t" \
|
||||
"ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
|
||||
"ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
|
||||
"wrpr %%g0, 0x94, %%pstate\n\t" \
|
||||
"mov %%l2, %%g6\n\t" \
|
||||
"ldx [%%g6 + %7], %%g4\n\t" \
|
||||
"ldx [%%g6 + %6], %%g4\n\t" \
|
||||
"wrpr %%g0, 0x96, %%pstate\n\t" \
|
||||
"andcc %%o7, %6, %%g0\n\t" \
|
||||
"beq,pt %%icc, 1f\n\t" \
|
||||
"brz,pt %%o7, 1f\n\t" \
|
||||
" mov %%g7, %0\n\t" \
|
||||
"b,a ret_from_syscall\n\t" \
|
||||
"1:\n\t" \
|
||||
: "=&r" (last) \
|
||||
: "0" (next->thread_info), \
|
||||
"i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_FLAGS), "i" (TI_CWP), \
|
||||
"i" (_TIF_NEWCHILD), "i" (TI_TASK) \
|
||||
"i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
|
||||
"i" (TI_CWP), "i" (TI_TASK) \
|
||||
: "cc", \
|
||||
"g1", "g2", "g3", "g7", \
|
||||
"l2", "l3", "l4", "l5", "l6", "l7", \
|
||||
|
||||
@ -47,7 +47,9 @@ struct thread_info {
|
||||
struct pt_regs *kregs;
|
||||
struct exec_domain *exec_domain;
|
||||
int preempt_count; /* 0 => preemptable, <0 => BUG */
|
||||
int __pad;
|
||||
__u8 new_child;
|
||||
__u8 syscall_noerror;
|
||||
__u16 __pad;
|
||||
|
||||
unsigned long *utraps;
|
||||
|
||||
@ -87,6 +89,8 @@ struct thread_info {
|
||||
#define TI_KREGS 0x00000028
|
||||
#define TI_EXEC_DOMAIN 0x00000030
|
||||
#define TI_PRE_COUNT 0x00000038
|
||||
#define TI_NEW_CHILD 0x0000003c
|
||||
#define TI_SYS_NOERROR 0x0000003d
|
||||
#define TI_UTRAPS 0x00000040
|
||||
#define TI_REG_WINDOW 0x00000048
|
||||
#define TI_RWIN_SPTRS 0x000003c8
|
||||
@ -219,10 +223,10 @@ register struct thread_info *current_thread_info_reg asm("g6");
|
||||
#define TIF_UNALIGNED 5 /* allowed to do unaligned accesses */
|
||||
#define TIF_NEWSIGNALS 6 /* wants new-style signals */
|
||||
#define TIF_32BIT 7 /* 32-bit binary */
|
||||
#define TIF_NEWCHILD 8 /* just-spawned child process */
|
||||
/* flag bit 8 is available */
|
||||
#define TIF_SECCOMP 9 /* secure computing */
|
||||
#define TIF_SYSCALL_AUDIT 10 /* syscall auditing active */
|
||||
#define TIF_SYSCALL_SUCCESS 11
|
||||
/* flag bit 11 is available */
|
||||
/* NOTE: Thread flags >= 12 should be ones we have no interest
|
||||
* in using in assembly, else we can't use the mask as
|
||||
* an immediate value in instructions such as andcc.
|
||||
@ -239,10 +243,8 @@ register struct thread_info *current_thread_info_reg asm("g6");
|
||||
#define _TIF_UNALIGNED (1<<TIF_UNALIGNED)
|
||||
#define _TIF_NEWSIGNALS (1<<TIF_NEWSIGNALS)
|
||||
#define _TIF_32BIT (1<<TIF_32BIT)
|
||||
#define _TIF_NEWCHILD (1<<TIF_NEWCHILD)
|
||||
#define _TIF_SECCOMP (1<<TIF_SECCOMP)
|
||||
#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
|
||||
#define _TIF_SYSCALL_SUCCESS (1<<TIF_SYSCALL_SUCCESS)
|
||||
#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
|
||||
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
|
||||
|
||||
|
||||
@ -9,49 +9,8 @@
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* How timers work:
|
||||
*
|
||||
* On uniprocessors we just use counter zero for the system wide
|
||||
* ticker, this performs thread scheduling, clock book keeping,
|
||||
* and runs timer based events. Previously we used the Ultra
|
||||
* %tick interrupt for this purpose.
|
||||
*
|
||||
* On multiprocessors we pick one cpu as the master level 10 tick
|
||||
* processor. Here this counter zero tick handles clock book
|
||||
* keeping and timer events only. Each Ultra has it's level
|
||||
* 14 %tick interrupt set to fire off as well, even the master
|
||||
* tick cpu runs this locally. This ticker performs thread
|
||||
* scheduling, system/user tick counting for the current thread,
|
||||
* and also profiling if enabled.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
/* Two timers, traditionally steered to PIL's 10 and 14 respectively.
|
||||
* But since INO packets are used on sun5, we could use any PIL level
|
||||
* we like, however for now we use the normal ones.
|
||||
*
|
||||
* The 'reg' and 'interrupts' properties for these live in nodes named
|
||||
* 'counter-timer'. The first of three 'reg' properties describe where
|
||||
* the sun5_timer registers are. The other two I have no idea. (XXX)
|
||||
*/
|
||||
struct sun5_timer {
|
||||
u64 count0;
|
||||
u64 limit0;
|
||||
u64 count1;
|
||||
u64 limit1;
|
||||
};
|
||||
|
||||
#define SUN5_LIMIT_ENABLE 0x80000000
|
||||
#define SUN5_LIMIT_TOZERO 0x40000000
|
||||
#define SUN5_LIMIT_ZRESTART 0x20000000
|
||||
#define SUN5_LIMIT_CMASK 0x1fffffff
|
||||
|
||||
/* Given a HZ value, set the limit register to so that the timer IRQ
|
||||
* gets delivered that often.
|
||||
*/
|
||||
#define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz))
|
||||
|
||||
struct sparc64_tick_ops {
|
||||
void (*init_tick)(unsigned long);
|
||||
unsigned long (*get_tick)(void);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user