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mt76x0: eeprom files
Add eeprom files of mt76x0 driver. Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Stanislaw Gruszka
Kalle Valo
parent
134b2d0d1f
commit
e87b503951
445
drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c
Normal file
445
drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c
Normal file
@ -0,0 +1,445 @@
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/*
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* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
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* Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/of.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/etherdevice.h>
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#include <asm/unaligned.h>
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#include "mt76x0.h"
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#include "eeprom.h"
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static bool
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field_valid(u8 val)
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{
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return val != 0xff;
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}
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static s8
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field_validate(u8 val)
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{
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if (!field_valid(val))
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return 0;
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return val;
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}
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static inline int
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sign_extend(u32 val, unsigned int size)
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{
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bool sign = val & BIT(size - 1);
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val &= BIT(size - 1) - 1;
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return sign ? val : -val;
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}
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static int
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mt76x0_efuse_read(struct mt76x0_dev *dev, u16 addr, u8 *data,
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enum mt76x0_eeprom_access_modes mode)
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{
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u32 val;
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int i;
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val = mt76_rr(dev, MT_EFUSE_CTRL);
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val &= ~(MT_EFUSE_CTRL_AIN |
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MT_EFUSE_CTRL_MODE);
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val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf) |
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FIELD_PREP(MT_EFUSE_CTRL_MODE, mode) |
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MT_EFUSE_CTRL_KICK;
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mt76_wr(dev, MT_EFUSE_CTRL, val);
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if (!mt76_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
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return -ETIMEDOUT;
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val = mt76_rr(dev, MT_EFUSE_CTRL);
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if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) {
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/* Parts of eeprom not in the usage map (0x80-0xc0,0xf0)
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* will not return valid data but it's ok.
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*/
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memset(data, 0xff, 16);
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return 0;
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}
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for (i = 0; i < 4; i++) {
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val = mt76_rr(dev, MT_EFUSE_DATA(i));
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put_unaligned_le32(val, data + 4 * i);
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}
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return 0;
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}
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static int
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mt76x0_efuse_physical_size_check(struct mt76x0_dev *dev)
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{
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const int map_reads = DIV_ROUND_UP(MT_EFUSE_USAGE_MAP_SIZE, 16);
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u8 data[map_reads * 16];
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int ret, i;
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u32 start = 0, end = 0, cnt_free;
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for (i = 0; i < map_reads; i++) {
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ret = mt76x0_efuse_read(dev, MT_EE_USAGE_MAP_START + i * 16,
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data + i * 16, MT_EE_PHYSICAL_READ);
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if (ret)
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return ret;
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}
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for (i = 0; i < MT_EFUSE_USAGE_MAP_SIZE; i++)
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if (!data[i]) {
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if (!start)
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start = MT_EE_USAGE_MAP_START + i;
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end = MT_EE_USAGE_MAP_START + i;
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}
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cnt_free = end - start + 1;
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if (MT_EFUSE_USAGE_MAP_SIZE - cnt_free < 5) {
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dev_err(dev->mt76.dev, "Error: your device needs default EEPROM file and this driver doesn't support it!\n");
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return -EINVAL;
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}
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return 0;
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}
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static void
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mt76x0_set_chip_cap(struct mt76x0_dev *dev, u8 *eeprom)
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{
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enum mt76x2_board_type { BOARD_TYPE_2GHZ = 1, BOARD_TYPE_5GHZ = 2 };
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u16 nic_conf0 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_0);
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u16 nic_conf1 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_1);
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dev_dbg(dev->mt76.dev, "NIC_CONF0: %04x NIC_CONF1: %04x\n", nic_conf0, nic_conf1);
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switch (FIELD_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, nic_conf0)) {
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case BOARD_TYPE_5GHZ:
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dev->ee->has_5ghz = true;
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break;
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case BOARD_TYPE_2GHZ:
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dev->ee->has_2ghz = true;
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break;
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default:
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dev->ee->has_2ghz = true;
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dev->ee->has_5ghz = true;
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break;
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}
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dev_dbg(dev->mt76.dev, "Has 2GHZ %d 5GHZ %d\n", dev->ee->has_2ghz, dev->ee->has_5ghz);
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if (!field_valid(nic_conf1 & 0xff))
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nic_conf1 &= 0xff00;
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if (nic_conf1 & MT_EE_NIC_CONF_1_HW_RF_CTRL)
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dev_err(dev->mt76.dev,
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"Error: this driver does not support HW RF ctrl\n");
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if (!field_valid(nic_conf0 >> 8))
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return;
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if (FIELD_GET(MT_EE_NIC_CONF_0_RX_PATH, nic_conf0) > 1 ||
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FIELD_GET(MT_EE_NIC_CONF_0_TX_PATH, nic_conf0) > 1)
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dev_err(dev->mt76.dev,
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"Error: device has more than 1 RX/TX stream!\n");
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dev->ee->pa_type = FIELD_GET(MT_EE_NIC_CONF_0_PA_TYPE, nic_conf0);
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dev_dbg(dev->mt76.dev, "PA Type %d\n", dev->ee->pa_type);
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}
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static int
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mt76x0_set_macaddr(struct mt76x0_dev *dev, const u8 *eeprom)
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{
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const void *src = eeprom + MT_EE_MAC_ADDR;
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ether_addr_copy(dev->macaddr, src);
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if (!is_valid_ether_addr(dev->macaddr)) {
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eth_random_addr(dev->macaddr);
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dev_info(dev->mt76.dev,
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"Invalid MAC address, using random address %pM\n",
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dev->macaddr);
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}
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mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
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mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4) |
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FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));
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return 0;
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}
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static void
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mt76x0_set_temp_offset(struct mt76x0_dev *dev, u8 *eeprom)
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{
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u8 temp = eeprom[MT_EE_TEMP_OFFSET];
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if (field_valid(temp))
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dev->ee->temp_off = sign_extend(temp, 8);
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else
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dev->ee->temp_off = -10;
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}
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static void
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mt76x0_set_country_reg(struct mt76x0_dev *dev, u8 *eeprom)
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{
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/* Note: - region 31 is not valid for mt76x0 (see rtmp_init.c)
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* - comments in rtmp_def.h are incorrect (see rt_channel.c)
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*/
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static const struct reg_channel_bounds chan_bounds[] = {
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/* EEPROM country regions 0 - 7 */
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{ 1, 11 }, { 1, 13 }, { 10, 2 }, { 10, 4 },
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{ 14, 1 }, { 1, 14 }, { 3, 7 }, { 5, 9 },
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/* EEPROM country regions 32 - 33 */
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{ 1, 11 }, { 1, 14 }
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};
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u8 val = eeprom[MT_EE_COUNTRY_REGION_2GHZ];
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int idx = -1;
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dev_dbg(dev->mt76.dev, "REG 2GHZ %u REG 5GHZ %u\n", val, eeprom[MT_EE_COUNTRY_REGION_5GHZ]);
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if (val < 8)
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idx = val;
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if (val > 31 && val < 33)
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idx = val - 32 + 8;
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if (idx != -1)
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dev_info(dev->mt76.dev,
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"EEPROM country region %02hhx (channels %hhd-%hhd)\n",
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val, chan_bounds[idx].start,
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chan_bounds[idx].start + chan_bounds[idx].num - 1);
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else
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idx = 5; /* channels 1 - 14 */
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dev->ee->reg = chan_bounds[idx];
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/* TODO: country region 33 is special - phy should be set to B-mode
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* before entering channel 14 (see sta/connect.c)
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*/
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}
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static void
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mt76x0_set_rf_freq_off(struct mt76x0_dev *dev, u8 *eeprom)
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{
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u8 comp;
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dev->ee->rf_freq_off = field_validate(eeprom[MT_EE_FREQ_OFFSET]);
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comp = field_validate(eeprom[MT_EE_FREQ_OFFSET_COMPENSATION]);
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if (comp & BIT(7))
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dev->ee->rf_freq_off -= comp & 0x7f;
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else
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dev->ee->rf_freq_off += comp;
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}
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static void
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mt76x0_set_lna_gain(struct mt76x0_dev *dev, u8 *eeprom)
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{
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s8 gain;
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dev->ee->lna_gain_2ghz = eeprom[MT_EE_LNA_GAIN_2GHZ];
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dev->ee->lna_gain_5ghz[0] = eeprom[MT_EE_LNA_GAIN_5GHZ_0];
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gain = eeprom[MT_EE_LNA_GAIN_5GHZ_1];
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if (gain == 0xff || gain == 0)
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dev->ee->lna_gain_5ghz[1] = dev->ee->lna_gain_5ghz[0];
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else
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dev->ee->lna_gain_5ghz[1] = gain;
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gain = eeprom[MT_EE_LNA_GAIN_5GHZ_2];
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if (gain == 0xff || gain == 0)
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dev->ee->lna_gain_5ghz[2] = dev->ee->lna_gain_5ghz[0];
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else
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dev->ee->lna_gain_5ghz[2] = gain;
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}
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static void
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mt76x0_set_rssi_offset(struct mt76x0_dev *dev, u8 *eeprom)
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{
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int i;
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s8 *rssi_offset = dev->ee->rssi_offset_2ghz;
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for (i = 0; i < 2; i++) {
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rssi_offset[i] = eeprom[MT_EE_RSSI_OFFSET + i];
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if (rssi_offset[i] < -10 || rssi_offset[i] > 10) {
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dev_warn(dev->mt76.dev,
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"Warning: EEPROM RSSI is invalid %02hhx\n",
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rssi_offset[i]);
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rssi_offset[i] = 0;
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}
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}
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rssi_offset = dev->ee->rssi_offset_5ghz;
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for (i = 0; i < 3; i++) {
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rssi_offset[i] = eeprom[MT_EE_RSSI_OFFSET_5GHZ + i];
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if (rssi_offset[i] < -10 || rssi_offset[i] > 10) {
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dev_warn(dev->mt76.dev,
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"Warning: EEPROM RSSI is invalid %02hhx\n",
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rssi_offset[i]);
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rssi_offset[i] = 0;
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}
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}
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}
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static u32
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calc_bw40_power_rate(u32 value, int delta)
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{
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u32 ret = 0;
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int i, tmp;
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for (i = 0; i < 4; i++) {
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tmp = s6_to_int((value >> i*8) & 0xff) + delta;
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ret |= (u32)(int_to_s6(tmp)) << i*8;
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}
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return ret;
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}
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static s8
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get_delta(u8 val)
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{
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s8 ret;
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if (!field_valid(val) || !(val & BIT(7)))
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return 0;
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ret = val & 0x1f;
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if (ret > 8)
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ret = 8;
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if (val & BIT(6))
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ret = -ret;
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return ret;
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}
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static void
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mt76x0_set_tx_power_per_rate(struct mt76x0_dev *dev, u8 *eeprom)
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{
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s8 bw40_delta_2g, bw40_delta_5g;
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u32 val;
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int i;
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bw40_delta_2g = get_delta(eeprom[MT_EE_TX_POWER_DELTA_BW40]);
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bw40_delta_5g = get_delta(eeprom[MT_EE_TX_POWER_DELTA_BW40 + 1]);
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for (i = 0; i < 5; i++) {
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val = get_unaligned_le32(eeprom + MT_EE_TX_POWER_BYRATE(i));
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/* Skip last 16 bits. */
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if (i == 4)
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val &= 0x0000ffff;
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dev->ee->tx_pwr_cfg_2g[i][0] = val;
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dev->ee->tx_pwr_cfg_2g[i][1] = calc_bw40_power_rate(val, bw40_delta_2g);
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}
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/* Reading per rate tx power for 5 GHz band is a bit more complex. Note
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* we mix 16 bit and 32 bit reads and sometimes do shifts.
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*/
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val = get_unaligned_le16(eeprom + 0x120);
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val <<= 16;
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dev->ee->tx_pwr_cfg_5g[0][0] = val;
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dev->ee->tx_pwr_cfg_5g[0][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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val = get_unaligned_le32(eeprom + 0x122);
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dev->ee->tx_pwr_cfg_5g[1][0] = val;
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dev->ee->tx_pwr_cfg_5g[1][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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val = get_unaligned_le16(eeprom + 0x126);
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dev->ee->tx_pwr_cfg_5g[2][0] = val;
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dev->ee->tx_pwr_cfg_5g[2][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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val = get_unaligned_le16(eeprom + 0xec);
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val <<= 16;
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dev->ee->tx_pwr_cfg_5g[3][0] = val;
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dev->ee->tx_pwr_cfg_5g[3][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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val = get_unaligned_le16(eeprom + 0xee);
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dev->ee->tx_pwr_cfg_5g[4][0] = val;
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dev->ee->tx_pwr_cfg_5g[4][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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}
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static void
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mt76x0_set_tx_power_per_chan(struct mt76x0_dev *dev, u8 *eeprom)
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{
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int i;
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u8 tx_pwr;
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for (i = 0; i < 14; i++) {
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tx_pwr = eeprom[MT_EE_TX_POWER_OFFSET_2GHZ + i];
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if (tx_pwr <= 0x3f && tx_pwr > 0)
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dev->ee->tx_pwr_per_chan[i] = tx_pwr;
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else
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dev->ee->tx_pwr_per_chan[i] = 5;
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}
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for (i = 0; i < 40; i++) {
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tx_pwr = eeprom[MT_EE_TX_POWER_OFFSET_5GHZ + i];
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if (tx_pwr <= 0x3f && tx_pwr > 0)
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dev->ee->tx_pwr_per_chan[14 + i] = tx_pwr;
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else
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dev->ee->tx_pwr_per_chan[14 + i] = 5;
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}
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dev->ee->tx_pwr_per_chan[54] = dev->ee->tx_pwr_per_chan[22];
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dev->ee->tx_pwr_per_chan[55] = dev->ee->tx_pwr_per_chan[28];
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dev->ee->tx_pwr_per_chan[56] = dev->ee->tx_pwr_per_chan[34];
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dev->ee->tx_pwr_per_chan[57] = dev->ee->tx_pwr_per_chan[44];
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}
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int
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mt76x0_eeprom_init(struct mt76x0_dev *dev)
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{
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u8 *eeprom;
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int i, ret;
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ret = mt76x0_efuse_physical_size_check(dev);
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if (ret)
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return ret;
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dev->ee = devm_kzalloc(dev->mt76.dev, sizeof(*dev->ee), GFP_KERNEL);
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if (!dev->ee)
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return -ENOMEM;
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eeprom = kmalloc(MT76X0_EEPROM_SIZE, GFP_KERNEL);
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if (!eeprom)
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return -ENOMEM;
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for (i = 0; i + 16 <= MT76X0_EEPROM_SIZE; i += 16) {
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ret = mt76x0_efuse_read(dev, i, eeprom + i, MT_EE_READ);
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if (ret)
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goto out;
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}
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if (eeprom[MT_EE_VERSION_EE] > MT76X0U_EE_MAX_VER)
|
||||
dev_warn(dev->mt76.dev,
|
||||
"Warning: unsupported EEPROM version %02hhx\n",
|
||||
eeprom[MT_EE_VERSION_EE]);
|
||||
dev_info(dev->mt76.dev, "EEPROM ver:%02hhx fae:%02hhx\n",
|
||||
eeprom[MT_EE_VERSION_EE], eeprom[MT_EE_VERSION_FAE]);
|
||||
|
||||
mt76x0_set_macaddr(dev, eeprom);
|
||||
mt76x0_set_chip_cap(dev, eeprom);
|
||||
mt76x0_set_country_reg(dev, eeprom);
|
||||
mt76x0_set_rf_freq_off(dev, eeprom);
|
||||
mt76x0_set_temp_offset(dev, eeprom);
|
||||
mt76x0_set_lna_gain(dev, eeprom);
|
||||
mt76x0_set_rssi_offset(dev, eeprom);
|
||||
dev->chainmask = 0x0101;
|
||||
|
||||
mt76x0_set_tx_power_per_rate(dev, eeprom);
|
||||
mt76x0_set_tx_power_per_chan(dev, eeprom);
|
||||
|
||||
out:
|
||||
kfree(eeprom);
|
||||
return ret;
|
||||
}
|
||||
149
drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h
Normal file
149
drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h
Normal file
@ -0,0 +1,149 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
|
||||
* Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MT76X0U_EEPROM_H
|
||||
#define __MT76X0U_EEPROM_H
|
||||
|
||||
struct mt76x0_dev;
|
||||
|
||||
#define MT76X0U_EE_MAX_VER 0x0c
|
||||
#define MT76X0_EEPROM_SIZE 512
|
||||
|
||||
#define MT76X0U_DEFAULT_TX_POWER 6
|
||||
|
||||
enum mt76_eeprom_field {
|
||||
MT_EE_CHIP_ID = 0x00,
|
||||
MT_EE_VERSION_FAE = 0x02,
|
||||
MT_EE_VERSION_EE = 0x03,
|
||||
MT_EE_MAC_ADDR = 0x04,
|
||||
MT_EE_NIC_CONF_0 = 0x34,
|
||||
MT_EE_NIC_CONF_1 = 0x36,
|
||||
MT_EE_COUNTRY_REGION_5GHZ = 0x38,
|
||||
MT_EE_COUNTRY_REGION_2GHZ = 0x39,
|
||||
MT_EE_FREQ_OFFSET = 0x3a,
|
||||
MT_EE_NIC_CONF_2 = 0x42,
|
||||
|
||||
MT_EE_LNA_GAIN_2GHZ = 0x44,
|
||||
MT_EE_LNA_GAIN_5GHZ_0 = 0x45,
|
||||
MT_EE_RSSI_OFFSET = 0x46,
|
||||
MT_EE_RSSI_OFFSET_5GHZ = 0x4a,
|
||||
MT_EE_LNA_GAIN_5GHZ_1 = 0x49,
|
||||
MT_EE_LNA_GAIN_5GHZ_2 = 0x4d,
|
||||
|
||||
MT_EE_TX_POWER_DELTA_BW40 = 0x50,
|
||||
|
||||
MT_EE_TX_POWER_OFFSET_2GHZ = 0x52,
|
||||
|
||||
MT_EE_TX_TSSI_SLOPE = 0x6e,
|
||||
MT_EE_TX_TSSI_OFFSET_GROUP = 0x6f,
|
||||
MT_EE_TX_TSSI_OFFSET = 0x76,
|
||||
|
||||
MT_EE_TX_POWER_OFFSET_5GHZ = 0x78,
|
||||
|
||||
MT_EE_TEMP_OFFSET = 0xd1,
|
||||
MT_EE_FREQ_OFFSET_COMPENSATION = 0xdb,
|
||||
MT_EE_TX_POWER_BYRATE_BASE = 0xde,
|
||||
|
||||
MT_EE_TX_POWER_BYRATE_BASE_5GHZ = 0x120,
|
||||
|
||||
MT_EE_USAGE_MAP_START = 0x1e0,
|
||||
MT_EE_USAGE_MAP_END = 0x1fc,
|
||||
};
|
||||
|
||||
#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)
|
||||
#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)
|
||||
#define MT_EE_NIC_CONF_0_PA_TYPE GENMASK(9, 8)
|
||||
#define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)
|
||||
|
||||
#define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0)
|
||||
#define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1)
|
||||
#define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2)
|
||||
#define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3)
|
||||
#define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13)
|
||||
|
||||
#define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0)
|
||||
#define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4)
|
||||
#define MT_EE_NIC_CONF_2_HW_ANTDIV BIT(8)
|
||||
#define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)
|
||||
#define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11)
|
||||
#define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13)
|
||||
|
||||
#define MT_EE_TX_POWER_BYRATE(i) (MT_EE_TX_POWER_BYRATE_BASE + \
|
||||
(i) * 4)
|
||||
|
||||
#define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \
|
||||
MT_EE_USAGE_MAP_START + 1)
|
||||
|
||||
enum mt76x0_eeprom_access_modes {
|
||||
MT_EE_READ = 0,
|
||||
MT_EE_PHYSICAL_READ = 1,
|
||||
};
|
||||
|
||||
struct reg_channel_bounds {
|
||||
u8 start;
|
||||
u8 num;
|
||||
};
|
||||
|
||||
struct mt76x0_eeprom_params {
|
||||
u8 rf_freq_off;
|
||||
s16 temp_off;
|
||||
s8 rssi_offset_2ghz[2];
|
||||
s8 rssi_offset_5ghz[3];
|
||||
s8 lna_gain_2ghz;
|
||||
s8 lna_gain_5ghz[3];
|
||||
u8 pa_type;
|
||||
|
||||
/* TX_PWR_CFG_* values from EEPROM for 20 and 40 Mhz bandwidths. */
|
||||
u32 tx_pwr_cfg_2g[5][2];
|
||||
u32 tx_pwr_cfg_5g[5][2];
|
||||
|
||||
u8 tx_pwr_per_chan[58];
|
||||
|
||||
struct reg_channel_bounds reg;
|
||||
|
||||
bool has_2ghz;
|
||||
bool has_5ghz;
|
||||
};
|
||||
|
||||
int mt76x0_eeprom_init(struct mt76x0_dev *dev);
|
||||
|
||||
static inline u32 s6_validate(u32 reg)
|
||||
{
|
||||
WARN_ON(reg & ~GENMASK(5, 0));
|
||||
return reg & GENMASK(5, 0);
|
||||
}
|
||||
|
||||
static inline int s6_to_int(u32 reg)
|
||||
{
|
||||
int s6;
|
||||
|
||||
s6 = s6_validate(reg);
|
||||
if (s6 & BIT(5))
|
||||
s6 -= BIT(6);
|
||||
|
||||
return s6;
|
||||
}
|
||||
|
||||
static inline u32 int_to_s6(int val)
|
||||
{
|
||||
if (val < -0x20)
|
||||
return 0x20;
|
||||
if (val > 0x1f)
|
||||
return 0x1f;
|
||||
|
||||
return val & 0x3f;
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user