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thunderbolt: Configure lanes when switch is initialized
Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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@ -19,3 +19,117 @@ int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid)
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return -EINVAL;
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return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4);
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}
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static int read_lc_desc(struct tb_switch *sw, u32 *desc)
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{
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if (!sw->cap_lc)
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return -EINVAL;
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return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1);
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}
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static int find_port_lc_cap(struct tb_port *port)
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{
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struct tb_switch *sw = port->sw;
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int start, phys, ret, size;
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u32 desc;
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ret = read_lc_desc(sw, &desc);
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if (ret)
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return ret;
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/* Start of port LC registers */
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start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
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size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
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phys = tb_phy_port_from_link(port->port);
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return sw->cap_lc + start + phys * size;
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}
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static int tb_lc_configure_lane(struct tb_port *port, bool configure)
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{
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bool upstream = tb_is_upstream_port(port);
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struct tb_switch *sw = port->sw;
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u32 ctrl, lane;
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int cap, ret;
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if (sw->generation < 2)
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return 0;
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cap = find_port_lc_cap(port);
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if (cap < 0)
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return cap;
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ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
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if (ret)
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return ret;
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/* Resolve correct lane */
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if (port->port % 2)
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lane = TB_LC_SX_CTRL_L1C;
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else
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lane = TB_LC_SX_CTRL_L2C;
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if (configure) {
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ctrl |= lane;
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if (upstream)
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ctrl |= TB_LC_SX_CTRL_UPSTREAM;
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} else {
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ctrl &= ~lane;
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if (upstream)
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ctrl &= ~TB_LC_SX_CTRL_UPSTREAM;
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}
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return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
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}
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/**
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* tb_lc_configure_link() - Let LC know about configured link
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* @sw: Switch that is being added
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*
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* Informs LC of both parent switch and @sw that there is established
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* link between the two.
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*/
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int tb_lc_configure_link(struct tb_switch *sw)
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{
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struct tb_port *up, *down;
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int ret;
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if (!sw->config.enabled || !tb_route(sw))
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return 0;
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up = tb_upstream_port(sw);
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down = tb_port_at(tb_route(sw), tb_to_switch(sw->dev.parent));
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/* Configure parent link toward this switch */
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ret = tb_lc_configure_lane(down, true);
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if (ret)
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return ret;
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/* Configure upstream link from this switch to the parent */
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ret = tb_lc_configure_lane(up, true);
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if (ret)
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tb_lc_configure_lane(down, false);
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return ret;
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}
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/**
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* tb_lc_unconfigure_link() - Let LC know about unconfigured link
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* @sw: Switch to unconfigure
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*
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* Informs LC of both parent switch and @sw that the link between the
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* two does not exist anymore.
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*/
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void tb_lc_unconfigure_link(struct tb_switch *sw)
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{
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struct tb_port *up, *down;
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if (sw->is_unplugged || !sw->config.enabled || !tb_route(sw))
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return;
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up = tb_upstream_port(sw);
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down = tb_port_at(tb_route(sw), tb_to_switch(sw->dev.parent));
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tb_lc_configure_lane(up, false);
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tb_lc_configure_lane(down, false);
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}
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@ -1276,6 +1276,10 @@ int tb_switch_configure(struct tb_switch *sw)
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if (ret)
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return ret;
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ret = tb_lc_configure_link(sw);
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if (ret)
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return ret;
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return tb_plug_events_active(sw, true);
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}
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@ -1486,6 +1490,7 @@ void tb_switch_remove(struct tb_switch *sw)
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if (!sw->is_unplugged)
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tb_plug_events_active(sw, false);
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tb_lc_unconfigure_link(sw);
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tb_switch_nvm_remove(sw);
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@ -1545,6 +1550,10 @@ int tb_switch_resume(struct tb_switch *sw)
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if (err)
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return err;
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err = tb_lc_configure_link(sw);
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if (err)
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return err;
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err = tb_plug_events_active(sw, true);
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if (err)
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return err;
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@ -465,6 +465,8 @@ int tb_drom_read(struct tb_switch *sw);
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int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid);
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int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid);
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int tb_lc_configure_link(struct tb_switch *sw);
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void tb_lc_unconfigure_link(struct tb_switch *sw);
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static inline int tb_route_length(u64 route)
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{
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@ -238,6 +238,17 @@ struct tb_regs_hop {
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} __packed;
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/* Common link controller registers */
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#define TB_LC_DESC 0x02
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#define TB_LC_DESC_SIZE_SHIFT 8
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#define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)
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#define TB_LC_DESC_PORT_SIZE_SHIFT 16
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#define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)
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#define TB_LC_FUSE 0x03
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/* Link controller registers */
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#define TB_LC_SX_CTRL 0x96
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#define TB_LC_SX_CTRL_L1C BIT(16)
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#define TB_LC_SX_CTRL_L2C BIT(20)
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#define TB_LC_SX_CTRL_UPSTREAM BIT(30)
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#endif
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