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ionic: clean interrupt before enabling queue to avoid credit race
Clear the interrupt credits before enabling the queue rather
than after to be sure that the enabled queue starts at 0 and
that we don't wipe away possible credits after enabling the
queue.
Fixes: 0f3154e6bc
("ionic: Add Tx and Rx handling")
Signed-off-by: Neel Patel <neel.patel@amd.com>
Signed-off-by: Shannon Nelson <shannon.nelson@amd.com>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
parent
69ff53e4a4
commit
e8797a0584
@ -269,6 +269,7 @@ static int ionic_qcq_enable(struct ionic_qcq *qcq)
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.oper = IONIC_Q_ENABLE,
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},
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};
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int ret;
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idev = &lif->ionic->idev;
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dev = lif->ionic->dev;
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@ -276,16 +277,24 @@ static int ionic_qcq_enable(struct ionic_qcq *qcq)
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dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
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ctx.cmd.q_control.index, ctx.cmd.q_control.type);
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if (qcq->flags & IONIC_QCQ_F_INTR)
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ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
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ret = ionic_adminq_post_wait(lif, &ctx);
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if (ret)
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return ret;
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if (qcq->napi.poll)
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napi_enable(&qcq->napi);
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if (qcq->flags & IONIC_QCQ_F_INTR) {
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irq_set_affinity_hint(qcq->intr.vector,
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&qcq->intr.affinity_mask);
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napi_enable(&qcq->napi);
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ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
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ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
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IONIC_INTR_MASK_CLEAR);
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}
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return ionic_adminq_post_wait(lif, &ctx);
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return 0;
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}
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static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err)
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