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MMC core:
- Fixup RPMB requests to use mrq->sbc when sending CMD23 MMC host: - omap: Fix broken MMC/SD on OMAP15XX/OMAP5910/OMAP310 - sdhci-omap: Fix DCRC error handling during tuning - sdhci: Fixup the timeout check window for clock and reset -----BEGIN PGP SIGNATURE----- iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAlwSOjAXHHVsZi5oYW5z c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjCkexA//cw/KotpQQpIirpmVvvnB52aR eephJ6CsoFC6Mqdmjto9i4hO4bwsDr0S8RQBjF+rpcGzN2lo3Kn6rongKxWd5Y++ UZkNdY/t8rGe/bumbaQgvMNnQ7RcwknlL36Xn2sN+hcoqY4/8P/3eF4+ysc4i4Gy PG6AHXVNotCmQwwCElAmhKoQN2JCMRZyUlMkgl/yXqLljhEQJ0jzWHicFFsRMF4t teCV3CGazffYopipiQUeRNKUbCTaF8UFoybgONnyVXFy9gmzzAAbb6behRbh2U/s XNqopa2R3wwxXep2TrwUDYMrDFl1ibRnuYi0VYz0VZRyA1vdEz8XKB3QQaQf03d2 yzjWUWd4YI0RZMrdhaOIyvVkbk9//2JzrCHen1wnhU8AFInpJdcwN0NKcVCUJXfb 5f2fB1GO9lDogW0n+z57+Hsux9wWWcLcfrY5g454qlySou/jmvfhH0onhQOH4aTs oJcU7vDsZQHftQYfol2e8K/5m3KKRKVRCDLzw0RRQbplC04r/5afuL3dA1YEI8/Y ZTAgd0rOXvOY+oW4q0a8CbEnknk9MoXUd41/LkbG8eJWliStOsV0PJZzmgDcIgPH EB3LyZRccJwKzSMtLLktx/iTm4grVjFABnQxlf80twoJjjnlcoNaBYHfr3Zc9BTf 7E7AXxdUUwMn5qWhOxQ= =wS1m -----END PGP SIGNATURE----- Merge tag 'mmc-v4.20-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull mmc fixes from Ulf Hansson: "MMC core: - Fixup RPMB requests to use mrq->sbc when sending CMD23 MMC host: - omap: Fix broken MMC/SD on OMAP15XX/OMAP5910/OMAP310 - sdhci-omap: Fix DCRC error handling during tuning - sdhci: Fixup the timeout check window for clock and reset" * tag 'mmc-v4.20-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci: fix the timeout check window for clock and reset mmc: sdhci-omap: Fix DCRC error handling during tuning MMC: OMAP: fix broken MMC on OMAP15XX/OMAP5910/OMAP310 mmc: core: use mrq->sbc when sending CMD23 for RPMB
This commit is contained in:
Linus Torvalds
commit
e861e11c59
@ -472,7 +472,7 @@ out:
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static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,
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struct mmc_blk_ioc_data *idata)
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{
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struct mmc_command cmd = {};
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struct mmc_command cmd = {}, sbc = {};
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struct mmc_data data = {};
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struct mmc_request mrq = {};
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struct scatterlist sg;
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@ -550,10 +550,15 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,
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}
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if (idata->rpmb) {
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err = mmc_set_blockcount(card, data.blocks,
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idata->ic.write_flag & (1 << 31));
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if (err)
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return err;
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sbc.opcode = MMC_SET_BLOCK_COUNT;
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/*
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* We don't do any blockcount validation because the max size
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* may be increased by a future standard. We just copy the
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* 'Reliable Write' bit here.
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*/
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sbc.arg = data.blocks | (idata->ic.write_flag & BIT(31));
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sbc.flags = MMC_RSP_R1 | MMC_CMD_AC;
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mrq.sbc = &sbc;
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}
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if ((MMC_EXTRACT_INDEX_FROM_ARG(cmd.arg) == EXT_CSD_SANITIZE_START) &&
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@ -104,6 +104,7 @@ struct mmc_omap_slot {
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unsigned int vdd;
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u16 saved_con;
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u16 bus_mode;
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u16 power_mode;
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unsigned int fclk_freq;
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struct tasklet_struct cover_tasklet;
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@ -1157,7 +1158,7 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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struct mmc_omap_slot *slot = mmc_priv(mmc);
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struct mmc_omap_host *host = slot->host;
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int i, dsor;
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int clk_enabled;
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int clk_enabled, init_stream;
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mmc_omap_select_slot(slot, 0);
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@ -1167,6 +1168,7 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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slot->vdd = ios->vdd;
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clk_enabled = 0;
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init_stream = 0;
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switch (ios->power_mode) {
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case MMC_POWER_OFF:
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mmc_omap_set_power(slot, 0, ios->vdd);
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@ -1174,13 +1176,17 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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case MMC_POWER_UP:
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/* Cannot touch dsor yet, just power up MMC */
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mmc_omap_set_power(slot, 1, ios->vdd);
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slot->power_mode = ios->power_mode;
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goto exit;
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case MMC_POWER_ON:
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mmc_omap_fclk_enable(host, 1);
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clk_enabled = 1;
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dsor |= 1 << 11;
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if (slot->power_mode != MMC_POWER_ON)
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init_stream = 1;
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break;
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}
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slot->power_mode = ios->power_mode;
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if (slot->bus_mode != ios->bus_mode) {
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if (slot->pdata->set_bus_mode != NULL)
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@ -1196,7 +1202,7 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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for (i = 0; i < 2; i++)
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OMAP_MMC_WRITE(host, CON, dsor);
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slot->saved_con = dsor;
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if (ios->power_mode == MMC_POWER_ON) {
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if (init_stream) {
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/* worst case at 400kHz, 80 cycles makes 200 microsecs */
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int usecs = 250;
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@ -1234,6 +1240,7 @@ static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
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slot->host = host;
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slot->mmc = mmc;
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slot->id = id;
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slot->power_mode = MMC_POWER_UNDEFINED;
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slot->pdata = &host->pdata->slots[id];
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host->slots[id] = slot;
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@ -288,9 +288,9 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
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struct device *dev = omap_host->dev;
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struct mmc_ios *ios = &mmc->ios;
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u32 start_window = 0, max_window = 0;
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bool dcrc_was_enabled = false;
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u8 cur_match, prev_match = 0;
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u32 length = 0, max_len = 0;
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u32 ier = host->ier;
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u32 phase_delay = 0;
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int ret = 0;
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u32 reg;
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@ -317,9 +317,10 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
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* during the tuning procedure. So disable it during the
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* tuning procedure.
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*/
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ier &= ~SDHCI_INT_DATA_CRC;
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sdhci_writel(host, ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
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if (host->ier & SDHCI_INT_DATA_CRC) {
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host->ier &= ~SDHCI_INT_DATA_CRC;
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dcrc_was_enabled = true;
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}
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while (phase_delay <= MAX_PHASE_DELAY) {
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sdhci_omap_set_dll(omap_host, phase_delay);
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@ -366,6 +367,9 @@ tuning_error:
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ret:
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sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
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/* Reenable forbidden interrupt */
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if (dcrc_was_enabled)
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host->ier |= SDHCI_INT_DATA_CRC;
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sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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return ret;
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@ -216,8 +216,12 @@ void sdhci_reset(struct sdhci_host *host, u8 mask)
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timeout = ktime_add_ms(ktime_get(), 100);
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/* hw clears the bit when it's done */
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while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
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if (ktime_after(ktime_get(), timeout)) {
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while (1) {
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bool timedout = ktime_after(ktime_get(), timeout);
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if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
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break;
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if (timedout) {
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pr_err("%s: Reset 0x%x never completed.\n",
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mmc_hostname(host->mmc), (int)mask);
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sdhci_dumpregs(host);
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@ -1608,9 +1612,13 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
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/* Wait max 20 ms */
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timeout = ktime_add_ms(ktime_get(), 20);
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
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& SDHCI_CLOCK_INT_STABLE)) {
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if (ktime_after(ktime_get(), timeout)) {
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while (1) {
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bool timedout = ktime_after(ktime_get(), timeout);
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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if (clk & SDHCI_CLOCK_INT_STABLE)
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break;
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if (timedout) {
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pr_err("%s: Internal clock never stabilised.\n",
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mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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