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AT91 fixes for 6.1

Browse Source 
It contains:
 - signal name fix for a pin on SAMA7G5
 - memory self-refresh fix for SAMA7G5 by avoid soft resetting AC
   DLL which can introduce glitches in RAM controller and lead to
   unexpected behavior
 - led support fix for lan966x-pcb8291 board by enabling sgpio node
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Merge tag 'at91-fixes-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes

AT91 fixes for 6.1

It contains:
- signal name fix for a pin on SAMA7G5
- memory self-refresh fix for SAMA7G5 by avoid soft resetting AC
  DLL which can introduce glitches in RAM controller and lead to
  unexpected behavior
- led support fix for lan966x-pcb8291 board by enabling sgpio node

* tag 'at91-fixes-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: at91: pm: avoid soft resetting AC DLL
  ARM: dts: lan966x: Enable sgpio on pcb8291
  ARM: dts: at91: sama7g5: fix signal name of pin PB2

Link: https://lore.kernel.org/r/20221110115411.180876-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-11-14 10:22:40 +01:00
commit e82b5b63c6
4 changed files with 31 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm/boot/dts/lan966x-pcb8291.dts
View File

@ -69,6 +69,12 @@
pins = "GPIO_35", "GPIO_36";
function = "can0_b";
};
sgpio_a_pins: sgpio-a-pins {
/* SCK, D0, D1, LD */
pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
function = "sgpio_a";
};
};
&can0 {
@ -118,6 +124,20 @@
status = "okay";
};
&sgpio {
pinctrl-0 = <&sgpio_a_pins>;
pinctrl-names = "default";
microchip,sgpio-port-ranges = <0 3>, <8 11>;
status = "okay";
gpio@0 {
ngpios = <64>;
};
gpio@1 {
ngpios = <64>;
};
};
&switch {
status = "okay";
};

2
arch/arm/boot/dts/sama7g5-pinfunc.h
View File

@ -261,7 +261,7 @@
#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1)
#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1)
#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1)
#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB2__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB3 35
#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0)
#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1)

7
arch/arm/mach-at91/pm_suspend.S
View File

@ -169,10 +169,15 @@ sr_ena_2:
cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
bne sr_ena_2
/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
/* Disable DX DLLs for non-backup modes. */
cmp r7, #AT91_PM_BACKUP
beq sr_ena_3
/* Do not soft reset the AC DLL. */
ldr tmp1, [r3, DDR3PHY_ACDLLCR]
bic tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
str tmp1, [r3, DDR3PHY_ACDLLCR]
/* Disable DX DLLs. */
ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS

5
include/soc/at91/sama7-ddr.h
View File

@ -26,7 +26,10 @@
#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
#define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
#define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */
#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */