mirror of
https://github.com/torvalds/linux.git
synced 2024-11-23 12:42:02 +00:00
Merge branches 'clk-spreadtrum', 'clk-stm32f', 'clk-stm32mp1', 'clk-hi655x' and 'clk-gpio' into clk-next
* clk-spreadtrum: clk: sprd: add RTC gate for SC9860 dt-bindings: clocks: add APB RTC gate for SC9860 * clk-stm32f: clk: stm32: Add clk entry for SDMMC2 on stm32F769 clk: stm32: Add DSI clock for STM32F469 Board clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK * clk-stm32mp1: clk: stm32: add configuration flags for each of the stm32 drivers clk: stm32mp1: add Debug clocks clk: stm32mp1: add MCO clocks clk: stm32mp1: add RTC clock clk: stm32mp1: add Peripheral & Kernel Clocks clk: stm32mp1: add Kernel timers clk: stm32mp1: add Sub System clocks clk: stm32mp1: add Post-dividers for PLL clk: stm32mp1: add PLL clocks clk: stm32mp1: add Source Clocks for PLLs clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillators clk: stm32mp1: Introduce STM32MP1 clock driver dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings * clk-hi655x: clk: enable hi655x common clk automatically * clk-gpio: clk: clk-gpio: Allow GPIO to sleep in set/get_parent
This commit is contained in:
Stephen Boyd
commit
e8121d9867
60
Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
Normal file
60
Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
Normal file
@ -0,0 +1,60 @@
|
||||
STMicroelectronics STM32 Peripheral Reset Clock Controller
|
||||
==========================================================
|
||||
|
||||
The RCC IP is both a reset and a clock controller.
|
||||
|
||||
RCC makes also power management (resume/supend and wakeup interrupt).
|
||||
|
||||
Please also refer to reset.txt for common reset controller binding usage.
|
||||
|
||||
Please also refer to clock-bindings.txt for common clock controller
|
||||
binding usage.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: "st,stm32mp1-rcc", "syscon"
|
||||
- reg: should be register base and length as documented in the datasheet
|
||||
- #clock-cells: 1, device nodes should specify the clock in their
|
||||
"clocks" property, containing a phandle to the clock device node,
|
||||
an index specifying the clock to use.
|
||||
- #reset-cells: Shall be 1
|
||||
- interrupts: Should contain a general interrupt line and a interrupt line
|
||||
to the wake-up of processor (CSTOP).
|
||||
|
||||
Example:
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "st,stm32mp1-rcc", "syscon";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 145 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
Specifying clocks
|
||||
=================
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/stm32mp1-clks.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Specifying softreset control of devices
|
||||
=======================================
|
||||
|
||||
Device nodes should specify the reset channel required in their "resets"
|
||||
property, containing a phandle to the reset device node and an index specifying
|
||||
which channel to use.
|
||||
The index is the bit number within the RCC registers bank, starting from RCC
|
||||
base address.
|
||||
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
||||
Where bit_offset is the bit offset within the register.
|
||||
|
||||
For example on STM32MP1, for LTDC reset:
|
||||
ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
|
||||
= 0x180 / 4 * 32 + 0 = 3072
|
||||
|
||||
The list of valid indices for STM32MP1 is available in:
|
||||
include/dt-bindings/reset-controller/stm32mp1-resets.h
|
||||
|
||||
This file implements defines like:
|
||||
#define LTDC_R 3072
|
||||
@ -55,8 +55,10 @@ config COMMON_CLK_RK808
|
||||
by control register.
|
||||
|
||||
config COMMON_CLK_HI655X
|
||||
tristate "Clock driver for Hi655x"
|
||||
depends on MFD_HI655X_PMIC || COMPILE_TEST
|
||||
tristate "Clock driver for Hi655x" if EXPERT
|
||||
depends on (MFD_HI655X_PMIC || COMPILE_TEST)
|
||||
depends on REGMAP
|
||||
default MFD_HI655X_PMIC
|
||||
---help---
|
||||
This driver supports the hi655x PMIC clock. This
|
||||
multi-function device has one fixed-rate oscillator, clocked
|
||||
@ -238,6 +240,26 @@ config COMMON_CLK_VC5
|
||||
This driver supports the IDT VersaClock 5 and VersaClock 6
|
||||
programmable clock generators.
|
||||
|
||||
config COMMON_CLK_STM32MP157
|
||||
def_bool COMMON_CLK && MACH_STM32MP157
|
||||
help
|
||||
---help---
|
||||
Support for stm32mp157 SoC family clocks
|
||||
|
||||
config COMMON_CLK_STM32F
|
||||
bool "Clock driver for stm32f4 and stm32f7 SoC families"
|
||||
depends on MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746
|
||||
help
|
||||
---help---
|
||||
Support for stm32f4 and stm32f7 SoC families clocks
|
||||
|
||||
config COMMON_CLK_STM32H7
|
||||
bool "Clock driver for stm32h7 SoC family"
|
||||
depends on MACH_STM32H743
|
||||
help
|
||||
---help---
|
||||
Support for stm32h7 SoC family clocks
|
||||
|
||||
source "drivers/clk/bcm/Kconfig"
|
||||
source "drivers/clk/hisilicon/Kconfig"
|
||||
source "drivers/clk/imgtec/Kconfig"
|
||||
|
||||
@ -45,8 +45,9 @@ obj-$(CONFIG_COMMON_CLK_SCPI) += clk-scpi.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
|
||||
obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o
|
||||
obj-$(CONFIG_ARCH_STM32) += clk-stm32h7.o
|
||||
obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o
|
||||
obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o
|
||||
obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
|
||||
obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
|
||||
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
|
||||
obj-$(CONFIG_ARCH_U300) += clk-u300.o
|
||||
|
||||
@ -73,14 +73,14 @@ static u8 clk_gpio_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gpio *clk = to_clk_gpio(hw);
|
||||
|
||||
return gpiod_get_value(clk->gpiod);
|
||||
return gpiod_get_value_cansleep(clk->gpiod);
|
||||
}
|
||||
|
||||
static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_gpio *clk = to_clk_gpio(hw);
|
||||
|
||||
gpiod_set_value(clk->gpiod, index);
|
||||
gpiod_set_value_cansleep(clk->gpiod, index);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -282,6 +282,7 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
|
||||
|
||||
{ STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
|
||||
{ STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
|
||||
{ STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
|
||||
{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
|
||||
{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
|
||||
{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
|
||||
@ -315,7 +316,7 @@ static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
|
||||
|
||||
static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
|
||||
0x0000000000000003ull,
|
||||
0x04f77f033e01c9ffull };
|
||||
0x04f77f833e01c9ffull };
|
||||
|
||||
static const u64 *stm32f4_gate_map;
|
||||
|
||||
@ -521,7 +522,7 @@ static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
|
||||
};
|
||||
|
||||
static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
|
||||
{ PLL, 50, { "pll", "pll-q", NULL } },
|
||||
{ PLL, 50, { "pll", "pll-q", "pll-r" } },
|
||||
{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
|
||||
{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
|
||||
};
|
||||
@ -1047,6 +1048,8 @@ static const char *rtc_parents[4] = {
|
||||
"no-clock", "lse", "lsi", "hse-rtc"
|
||||
};
|
||||
|
||||
static const char *dsi_parent[2] = { NULL, "pll-r" };
|
||||
|
||||
static const char *lcd_parent[1] = { "pllsai-r-div" };
|
||||
|
||||
static const char *i2s_parents[2] = { "plli2s-r", NULL };
|
||||
@ -1156,6 +1159,12 @@ static const struct stm32_aux_clk stm32f469_aux_clk[] = {
|
||||
NO_GATE, 0,
|
||||
0
|
||||
},
|
||||
{
|
||||
CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
|
||||
STM32F4_RCC_DCKCFGR, 29, 1,
|
||||
STM32F4_RCC_APB2ENR, 27,
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
|
||||
},
|
||||
};
|
||||
|
||||
static const struct stm32_aux_clk stm32f746_aux_clk[] = {
|
||||
@ -1450,6 +1459,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
|
||||
stm32f4_gate_map = data->gates_map;
|
||||
|
||||
hse_clk = of_clk_get_parent_name(np, 0);
|
||||
dsi_parent[0] = hse_clk;
|
||||
|
||||
i2s_in_clk = of_clk_get_parent_name(np, 1);
|
||||
|
||||
|
||||
2117
drivers/clk/clk-stm32mp1.c
Normal file
2117
drivers/clk/clk-stm32mp1.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -959,6 +959,44 @@ static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c,
|
||||
0x1000, BIT(6), 0, 0);
|
||||
static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c,
|
||||
0x1000, BIT(9), 0, 0);
|
||||
static SPRD_SC_GATE_CLK(arch_rtc_eb, "arch-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(kpb_rtc_eb, "kpb-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(aon_syst_rtc_eb, "aon-syst-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(ap_syst_rtc_eb, "ap-syst-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(eic_rtc_eb, "eic-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(eic_rtcdv5_eb, "eic-rtcdv5-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(dcxo_tmr_rtc_eb, "dcxo-tmr-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(bb_cal_rtc_eb, "bb-cal-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(avs_big_rtc_eb, "avs-big-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(avs_lit_rtc_eb, "avs-lit-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(avs_gpu0_rtc_eb, "avs-gpu0-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(avs_gpu1_rtc_eb, "avs-gpu1-rtc-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(gpu_ts_eb, "gpu-ts-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
|
||||
static SPRD_SC_GATE_CLK(rtcdv10_eb, "rtcdv10-eb", "aon-apb", 0x10,
|
||||
0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
|
||||
|
||||
static struct sprd_clk_common *sc9860_aon_gate[] = {
|
||||
/* address base is 0x402e0000 */
|
||||
@ -1030,6 +1068,25 @@ static struct sprd_clk_common *sc9860_aon_gate[] = {
|
||||
&sdio1_2x_en.common,
|
||||
&sdio2_2x_en.common,
|
||||
&emmc_2x_en.common,
|
||||
&arch_rtc_eb.common,
|
||||
&kpb_rtc_eb.common,
|
||||
&aon_syst_rtc_eb.common,
|
||||
&ap_syst_rtc_eb.common,
|
||||
&aon_tmr_rtc_eb.common,
|
||||
&ap_tmr0_rtc_eb.common,
|
||||
&eic_rtc_eb.common,
|
||||
&eic_rtcdv5_eb.common,
|
||||
&ap_wdg_rtc_eb.common,
|
||||
&ap_tmr1_rtc_eb.common,
|
||||
&ap_tmr2_rtc_eb.common,
|
||||
&dcxo_tmr_rtc_eb.common,
|
||||
&bb_cal_rtc_eb.common,
|
||||
&avs_big_rtc_eb.common,
|
||||
&avs_lit_rtc_eb.common,
|
||||
&avs_gpu0_rtc_eb.common,
|
||||
&avs_gpu1_rtc_eb.common,
|
||||
&gpu_ts_eb.common,
|
||||
&rtcdv10_eb.common,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
|
||||
@ -1102,6 +1159,25 @@ static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
|
||||
[CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw,
|
||||
[CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw,
|
||||
[CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw,
|
||||
[CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw,
|
||||
[CLK_KPB_RTC_EB] = &kpb_rtc_eb.common.hw,
|
||||
[CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw,
|
||||
[CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw,
|
||||
[CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw,
|
||||
[CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw,
|
||||
[CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw,
|
||||
[CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw,
|
||||
[CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw,
|
||||
[CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw,
|
||||
[CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw,
|
||||
[CLK_DCXO_TMR_RTC_EB] = &dcxo_tmr_rtc_eb.common.hw,
|
||||
[CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw,
|
||||
[CLK_AVS_BIG_RTC_EB] = &avs_big_rtc_eb.common.hw,
|
||||
[CLK_AVS_LIT_RTC_EB] = &avs_lit_rtc_eb.common.hw,
|
||||
[CLK_AVS_GPU0_RTC_EB] = &avs_gpu0_rtc_eb.common.hw,
|
||||
[CLK_AVS_GPU1_RTC_EB] = &avs_gpu1_rtc_eb.common.hw,
|
||||
[CLK_GPU_TS_EB] = &gpu_ts_eb.common.hw,
|
||||
[CLK_RTCDV10_EB] = &rtcdv10_eb.common.hw,
|
||||
},
|
||||
.num = CLK_AON_GATE_NUM,
|
||||
};
|
||||
|
||||
@ -229,7 +229,26 @@
|
||||
#define CLK_SDIO1_2X_EN 65
|
||||
#define CLK_SDIO2_2X_EN 66
|
||||
#define CLK_EMMC_2X_EN 67
|
||||
#define CLK_AON_GATE_NUM (CLK_EMMC_2X_EN + 1)
|
||||
#define CLK_ARCH_RTC_EB 68
|
||||
#define CLK_KPB_RTC_EB 69
|
||||
#define CLK_AON_SYST_RTC_EB 70
|
||||
#define CLK_AP_SYST_RTC_EB 71
|
||||
#define CLK_AON_TMR_RTC_EB 72
|
||||
#define CLK_AP_TMR0_RTC_EB 73
|
||||
#define CLK_EIC_RTC_EB 74
|
||||
#define CLK_EIC_RTCDV5_EB 75
|
||||
#define CLK_AP_WDG_RTC_EB 76
|
||||
#define CLK_AP_TMR1_RTC_EB 77
|
||||
#define CLK_AP_TMR2_RTC_EB 78
|
||||
#define CLK_DCXO_TMR_RTC_EB 79
|
||||
#define CLK_BB_CAL_RTC_EB 80
|
||||
#define CLK_AVS_BIG_RTC_EB 81
|
||||
#define CLK_AVS_LIT_RTC_EB 82
|
||||
#define CLK_AVS_GPU0_RTC_EB 83
|
||||
#define CLK_AVS_GPU1_RTC_EB 84
|
||||
#define CLK_GPU_TS_EB 85
|
||||
#define CLK_RTCDV10_EB 86
|
||||
#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1)
|
||||
|
||||
#define CLK_LIT_MCU 0
|
||||
#define CLK_BIG_MCU 1
|
||||
|
||||
@ -33,11 +33,12 @@
|
||||
#define CLK_SAI2 11
|
||||
#define CLK_I2SQ_PDIV 12
|
||||
#define CLK_SAIQ_PDIV 13
|
||||
|
||||
#define END_PRIMARY_CLK 14
|
||||
|
||||
#define CLK_HSI 14
|
||||
#define CLK_SYSCLK 15
|
||||
#define CLK_F469_DSI 16
|
||||
|
||||
#define END_PRIMARY_CLK 17
|
||||
|
||||
#define CLK_HDMI_CEC 16
|
||||
#define CLK_SPDIF 17
|
||||
#define CLK_USART1 18
|
||||
|
||||
254
include/dt-bindings/clock/stm32mp1-clks.h
Normal file
254
include/dt-bindings/clock/stm32mp1-clks.h
Normal file
@ -0,0 +1,254 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
|
||||
#define _DT_BINDINGS_STM32MP1_CLKS_H_
|
||||
|
||||
/* OSCILLATOR clocks */
|
||||
#define CK_HSE 0
|
||||
#define CK_CSI 1
|
||||
#define CK_LSI 2
|
||||
#define CK_LSE 3
|
||||
#define CK_HSI 4
|
||||
#define CK_HSE_DIV2 5
|
||||
|
||||
/* Bus clocks */
|
||||
#define TIM2 6
|
||||
#define TIM3 7
|
||||
#define TIM4 8
|
||||
#define TIM5 9
|
||||
#define TIM6 10
|
||||
#define TIM7 11
|
||||
#define TIM12 12
|
||||
#define TIM13 13
|
||||
#define TIM14 14
|
||||
#define LPTIM1 15
|
||||
#define SPI2 16
|
||||
#define SPI3 17
|
||||
#define USART2 18
|
||||
#define USART3 19
|
||||
#define UART4 20
|
||||
#define UART5 21
|
||||
#define UART7 22
|
||||
#define UART8 23
|
||||
#define I2C1 24
|
||||
#define I2C2 25
|
||||
#define I2C3 26
|
||||
#define I2C5 27
|
||||
#define SPDIF 28
|
||||
#define CEC 29
|
||||
#define DAC12 30
|
||||
#define MDIO 31
|
||||
#define TIM1 32
|
||||
#define TIM8 33
|
||||
#define TIM15 34
|
||||
#define TIM16 35
|
||||
#define TIM17 36
|
||||
#define SPI1 37
|
||||
#define SPI4 38
|
||||
#define SPI5 39
|
||||
#define USART6 40
|
||||
#define SAI1 41
|
||||
#define SAI2 42
|
||||
#define SAI3 43
|
||||
#define DFSDM 44
|
||||
#define FDCAN 45
|
||||
#define LPTIM2 46
|
||||
#define LPTIM3 47
|
||||
#define LPTIM4 48
|
||||
#define LPTIM5 49
|
||||
#define SAI4 50
|
||||
#define SYSCFG 51
|
||||
#define VREF 52
|
||||
#define TMPSENS 53
|
||||
#define PMBCTRL 54
|
||||
#define HDP 55
|
||||
#define LTDC 56
|
||||
#define DSI 57
|
||||
#define IWDG2 58
|
||||
#define USBPHY 59
|
||||
#define STGENRO 60
|
||||
#define SPI6 61
|
||||
#define I2C4 62
|
||||
#define I2C6 63
|
||||
#define USART1 64
|
||||
#define RTCAPB 65
|
||||
#define TZC 66
|
||||
#define TZPC 67
|
||||
#define IWDG1 68
|
||||
#define BSEC 69
|
||||
#define STGEN 70
|
||||
#define DMA1 71
|
||||
#define DMA2 72
|
||||
#define DMAMUX 73
|
||||
#define ADC12 74
|
||||
#define USBO 75
|
||||
#define SDMMC3 76
|
||||
#define DCMI 77
|
||||
#define CRYP2 78
|
||||
#define HASH2 79
|
||||
#define RNG2 80
|
||||
#define CRC2 81
|
||||
#define HSEM 82
|
||||
#define IPCC 83
|
||||
#define GPIOA 84
|
||||
#define GPIOB 85
|
||||
#define GPIOC 86
|
||||
#define GPIOD 87
|
||||
#define GPIOE 88
|
||||
#define GPIOF 89
|
||||
#define GPIOG 90
|
||||
#define GPIOH 91
|
||||
#define GPIOI 92
|
||||
#define GPIOJ 93
|
||||
#define GPIOK 94
|
||||
#define GPIOZ 95
|
||||
#define CRYP1 96
|
||||
#define HASH1 97
|
||||
#define RNG1 98
|
||||
#define BKPSRAM 99
|
||||
#define MDMA 100
|
||||
#define GPU 101
|
||||
#define ETHCK 102
|
||||
#define ETHTX 103
|
||||
#define ETHRX 104
|
||||
#define ETHMAC 105
|
||||
#define FMC 106
|
||||
#define QSPI 107
|
||||
#define SDMMC1 108
|
||||
#define SDMMC2 109
|
||||
#define CRC1 110
|
||||
#define USBH 111
|
||||
#define ETHSTP 112
|
||||
|
||||
/* Kernel clocks */
|
||||
#define SDMMC1_K 118
|
||||
#define SDMMC2_K 119
|
||||
#define SDMMC3_K 120
|
||||
#define FMC_K 121
|
||||
#define QSPI_K 122
|
||||
#define ETHCK_K 123
|
||||
#define RNG1_K 124
|
||||
#define RNG2_K 125
|
||||
#define GPU_K 126
|
||||
#define USBPHY_K 127
|
||||
#define STGEN_K 128
|
||||
#define SPDIF_K 129
|
||||
#define SPI1_K 130
|
||||
#define SPI2_K 131
|
||||
#define SPI3_K 132
|
||||
#define SPI4_K 133
|
||||
#define SPI5_K 134
|
||||
#define SPI6_K 135
|
||||
#define CEC_K 136
|
||||
#define I2C1_K 137
|
||||
#define I2C2_K 138
|
||||
#define I2C3_K 139
|
||||
#define I2C4_K 140
|
||||
#define I2C5_K 141
|
||||
#define I2C6_K 142
|
||||
#define LPTIM1_K 143
|
||||
#define LPTIM2_K 144
|
||||
#define LPTIM3_K 145
|
||||
#define LPTIM4_K 146
|
||||
#define LPTIM5_K 147
|
||||
#define USART1_K 148
|
||||
#define USART2_K 149
|
||||
#define USART3_K 150
|
||||
#define UART4_K 151
|
||||
#define UART5_K 152
|
||||
#define USART6_K 153
|
||||
#define UART7_K 154
|
||||
#define UART8_K 155
|
||||
#define DFSDM_K 156
|
||||
#define FDCAN_K 157
|
||||
#define SAI1_K 158
|
||||
#define SAI2_K 159
|
||||
#define SAI3_K 160
|
||||
#define SAI4_K 161
|
||||
#define ADC12_K 162
|
||||
#define DSI_K 163
|
||||
#define DSI_PX 164
|
||||
#define ADFSDM_K 165
|
||||
#define USBO_K 166
|
||||
#define LTDC_PX 167
|
||||
#define DAC12_K 168
|
||||
#define ETHPTP_K 169
|
||||
|
||||
/* PLL */
|
||||
#define PLL1 176
|
||||
#define PLL2 177
|
||||
#define PLL3 178
|
||||
#define PLL4 179
|
||||
|
||||
/* ODF */
|
||||
#define PLL1_P 180
|
||||
#define PLL1_Q 181
|
||||
#define PLL1_R 182
|
||||
#define PLL2_P 183
|
||||
#define PLL2_Q 184
|
||||
#define PLL2_R 185
|
||||
#define PLL3_P 186
|
||||
#define PLL3_Q 187
|
||||
#define PLL3_R 188
|
||||
#define PLL4_P 189
|
||||
#define PLL4_Q 190
|
||||
#define PLL4_R 191
|
||||
|
||||
/* AUX */
|
||||
#define RTC 192
|
||||
|
||||
/* MCLK */
|
||||
#define CK_PER 193
|
||||
#define CK_MPU 194
|
||||
#define CK_AXI 195
|
||||
#define CK_MCU 196
|
||||
|
||||
/* Time base */
|
||||
#define TIM2_K 197
|
||||
#define TIM3_K 198
|
||||
#define TIM4_K 199
|
||||
#define TIM5_K 200
|
||||
#define TIM6_K 201
|
||||
#define TIM7_K 202
|
||||
#define TIM12_K 203
|
||||
#define TIM13_K 204
|
||||
#define TIM14_K 205
|
||||
#define TIM1_K 206
|
||||
#define TIM8_K 207
|
||||
#define TIM15_K 208
|
||||
#define TIM16_K 209
|
||||
#define TIM17_K 210
|
||||
|
||||
/* MCO clocks */
|
||||
#define CK_MCO1 211
|
||||
#define CK_MCO2 212
|
||||
|
||||
/* TRACE & DEBUG clocks */
|
||||
#define DBG 213
|
||||
#define CK_DBG 214
|
||||
#define CK_TRACE 215
|
||||
|
||||
/* DDR */
|
||||
#define DDRC1 220
|
||||
#define DDRC1LP 221
|
||||
#define DDRC2 222
|
||||
#define DDRC2LP 223
|
||||
#define DDRPHYC 224
|
||||
#define DDRPHYCLP 225
|
||||
#define DDRCAPB 226
|
||||
#define DDRCAPBLP 227
|
||||
#define AXIDCG 228
|
||||
#define DDRPHYCAPB 229
|
||||
#define DDRPHYCAPBLP 230
|
||||
#define DDRPERFM 231
|
||||
|
||||
#define STM32MP1_LAST_CLK 232
|
||||
|
||||
#define LTDC_K LTDC_PX
|
||||
#define ETHMAC_K ETHCK_K
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
|
||||
Loading…
Reference in New Issue
Block a user