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i2c: rcar: enable interrupts before starting transfer

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We want to enable the interrupts _before_ starting the transfer because
it is good programming style and also the proposed order in the R-Car
manual. There is no difference in practice because it doesn't matter in
which order both conditions appear if we wait for both to happen.

Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Wolfram Sang 2021-09-15 15:48:27 +02:00 committed by Wolfram Sang
parent c073b25dad
commit e7f4264821
1 changed files with 3 additions and 3 deletions
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6
drivers/i2c/busses/i2c-rcar.c
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@ -339,6 +339,9 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
priv->flags |= ID_LAST_MSG; priv->flags |= ID_LAST_MSG;
rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
if (!priv->atomic_xfer)
rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
/* /*
* We don't have a test case but the HW engineers say that the write order * We don't have a test case but the HW engineers say that the write order
* of ICMSR and ICMCR depends on whether we issue START or REP_START. Since * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
@ -354,9 +357,6 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
rcar_i2c_write(priv, ICMSR, 0); rcar_i2c_write(priv, ICMSR, 0);
} }
if (!priv->atomic_xfer)
rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
} }
static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)