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ASoC: stm32: Add full duplex support to i2s
This patch allows to use i2s interface either as single audio path (rx or tx), or bidirectional audio path. This patch is added separately, as the driver does not follow recommended use of the interface, to support this configuration. Signed-off-by: olivier moysan <olivier.moysan@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -489,7 +489,6 @@ static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
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struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
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int format = params_width(params);
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u32 cfgr, cfgr_mask, cfg1, cfg1_mask;
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bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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unsigned int fthlv;
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int ret;
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@ -515,19 +514,13 @@ static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
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}
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if (STM32_I2S_IS_SLAVE(i2s)) {
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if (playback_flg)
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cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_TX_SLAVE);
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else
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cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_RX_SLAVE);
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cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
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/* As data length is either 16 or 32 bits, fixch always set */
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cfgr |= I2S_CGFR_FIXCH;
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cfgr_mask |= I2S_CGFR_FIXCH;
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} else {
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if (playback_flg)
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cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_TX_MASTER);
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else
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cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_RX_MASTER);
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cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
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}
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cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
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@ -536,9 +529,7 @@ static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
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if (ret < 0)
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return ret;
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cfg1 = I2S_CFG1_RXDMAEN;
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if (playback_flg)
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cfg1 = I2S_CFG1_TXDMAEN;
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cfg1 = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
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cfg1_mask = cfg1;
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fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
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@ -553,32 +544,15 @@ static int stm32_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
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int ret, ier;
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i2s->substream = substream;
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spin_lock(&i2s->lock_fd);
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if (i2s->refcount) {
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dev_err(cpu_dai->dev, "%s stream already started\n",
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(substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
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"Capture" : "Playback"));
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spin_unlock(&i2s->lock_fd);
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return -EBUSY;
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}
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i2s->refcount = 1;
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i2s->refcount++;
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spin_unlock(&i2s->lock_fd);
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ret = regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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I2S_IFCR_MASK, I2S_IFCR_MASK);
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if (ret < 0)
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return ret;
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/* Enable ITs */
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ier = I2S_IER_OVRIE | I2S_IER_UDRIE;
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if (STM32_I2S_IS_SLAVE(i2s))
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ier |= I2S_IER_TIFREIE;
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return regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
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return regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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I2S_IFCR_MASK, I2S_IFCR_MASK);
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}
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static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
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@ -605,7 +579,7 @@ static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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{
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struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
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bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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u32 cfg1_mask;
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u32 cfg1_mask, ier;
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int ret;
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switch (cmd) {
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@ -628,10 +602,48 @@ static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
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return ret;
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}
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regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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I2S_IFCR_MASK, I2S_IFCR_MASK);
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if (playback_flg) {
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ier = I2S_IER_UDRIE;
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} else {
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ier = I2S_IER_OVRIE;
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spin_lock(&i2s->lock_fd);
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if (i2s->refcount == 1)
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/* dummy write to trigger capture */
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regmap_write(i2s->regmap,
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STM32_I2S_TXDR_REG, 0);
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spin_unlock(&i2s->lock_fd);
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}
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if (STM32_I2S_IS_SLAVE(i2s))
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ier |= I2S_IER_TIFREIE;
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regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (playback_flg)
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regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
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I2S_IER_UDRIE,
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(unsigned int)~I2S_IER_UDRIE);
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else
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regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
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I2S_IER_OVRIE,
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(unsigned int)~I2S_IER_OVRIE);
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spin_lock(&i2s->lock_fd);
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i2s->refcount--;
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if (i2s->refcount) {
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spin_unlock(&i2s->lock_fd);
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break;
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}
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spin_unlock(&i2s->lock_fd);
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dev_dbg(cpu_dai->dev, "stop I2S\n");
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ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
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@ -641,10 +653,7 @@ static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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return ret;
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}
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cfg1_mask = I2S_CFG1_RXDMAEN;
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if (playback_flg)
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cfg1_mask = I2S_CFG1_TXDMAEN;
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cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
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regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
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cfg1_mask, 0);
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break;
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@ -662,10 +671,6 @@ static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
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i2s->substream = NULL;
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spin_lock(&i2s->lock_fd);
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i2s->refcount = 0;
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spin_unlock(&i2s->lock_fd);
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regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
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}
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