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MIPS: TXx9: Do PCI error checks on own line

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Instead of if conditions with line splits, use the usual error handling
pattern with a separate variable to improve readability.

The second check can use reverse logic which reduces indentation level.

No functional changes intended.

Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Ilpo Järvinen 2023-08-27 16:36:59 +03:00 committed by Thomas Bogendoerfer
parent d913ff5611
commit e7513eccb7
1 changed files with 23 additions and 20 deletions
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43
arch/mips/txx9/generic/pci.c
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@ -51,6 +51,7 @@ int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
unsigned short vid;
int cap66 = -1;
u16 stat;
int ret;
/* It seems SLC90E66 needs some time after PCI reset... */
mdelay(80);
@ -60,9 +61,9 @@ int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
if (PCI_FUNC(pci_devfn))
continue;
if (early_read_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_VENDOR_ID, &vid) !=
PCIBIOS_SUCCESSFUL)
ret = early_read_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_VENDOR_ID, &vid);
if (ret != PCIBIOS_SUCCESSFUL)
continue;
if (vid == 0xffff)
continue;
@ -343,26 +344,28 @@ static void tc35815_fixup(struct pci_dev *dev)
static void final_fixup(struct pci_dev *dev)
{
unsigned long timeout;
unsigned char bist;
int ret;
/* Do build-in self test */
if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
(bist & PCI_BIST_CAPABLE)) {
unsigned long timeout;
pci_set_power_state(dev, PCI_D0);
pr_info("PCI: %s BIST...", pci_name(dev));
pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
timeout = jiffies + HZ * 2; /* timeout after 2 sec */
do {
pci_read_config_byte(dev, PCI_BIST, &bist);
if (time_after(jiffies, timeout))
break;
} while (bist & PCI_BIST_START);
if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
pr_cont("failed. (0x%x)\n", bist);
else
pr_cont("OK.\n");
}
ret = pci_read_config_byte(dev, PCI_BIST, &bist);
if ((ret != PCIBIOS_SUCCESSFUL) || !(bist & PCI_BIST_CAPABLE))
return;
pci_set_power_state(dev, PCI_D0);
pr_info("PCI: %s BIST...", pci_name(dev));
pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
timeout = jiffies + HZ * 2; /* timeout after 2 sec */
do {
pci_read_config_byte(dev, PCI_BIST, &bist);
if (time_after(jiffies, timeout))
break;
} while (bist & PCI_BIST_START);
if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
pr_cont("failed. (0x%x)\n", bist);
else
pr_cont("OK.\n");
}
#ifdef CONFIG_TOSHIBA_FPCIB0