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Merge branch 'for-next/perf-cn10k' into for-next/perf
* for-next/perf-cn10k: dt-bindings: perf: Add YAML schemas for Marvell CN10K LLC-TAD pmu bindings drivers: perf: Add LLC-TAD perf counter support
This commit is contained in:
Will Deacon
commit
e73bc4fd78
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@ -0,0 +1,63 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell CN10K LLC-TAD performance monitor
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maintainers:
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- Bhaskara Budiredla <bbudiredla@marvell.com>
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description: |
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The Tag-and-Data units (TADs) maintain coherence and contain CN10K
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shared on-chip last level cache (LLC). The tad pmu measures the
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performance of last-level cache. Each tad pmu supports up to eight
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counters.
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The DT setup comprises of number of tad blocks, the sizes of pmu
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regions, tad blocks and overall base address of the HW.
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properties:
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compatible:
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const: marvell,cn10k-tad-pmu
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reg:
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maxItems: 1
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marvell,tad-cnt:
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description: specifies the number of tads on the soc
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$ref: /schemas/types.yaml#/definitions/uint32
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marvell,tad-page-size:
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description: specifies the size of each tad page
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$ref: /schemas/types.yaml#/definitions/uint32
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marvell,tad-pmu-page-size:
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description: specifies the size of page that the pmu uses
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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- compatible
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- reg
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- marvell,tad-cnt
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- marvell,tad-page-size
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- marvell,tad-pmu-page-size
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additionalProperties: false
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examples:
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- |
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tad {
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#address-cells = <2>;
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#size-cells = <2>;
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tad_pmu@80000000 {
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compatible = "marvell,cn10k-tad-pmu";
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reg = <0x87e2 0x80000000 0x0 0x1000>;
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marvell,tad-cnt = <1>;
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marvell,tad-page-size = <0x1000>;
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marvell,tad-pmu-page-size = <0x1000>;
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};
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};
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@ -139,6 +139,13 @@ config ARM_DMC620_PMU
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Support for PMU events monitoring on the ARM DMC-620 memory
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controller.
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config MARVELL_CN10K_TAD_PMU
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tristate "Marvell CN10K LLC-TAD PMU"
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depends on ARM64 || (COMPILE_TEST && 64BIT)
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help
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Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
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performance monitors on CN10K family silicons.
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source "drivers/perf/hisilicon/Kconfig"
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endmenu
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@ -14,3 +14,4 @@ obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o
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obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
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obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
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obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o
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obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o
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|
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429
drivers/perf/marvell_cn10k_tad_pmu.c
Normal file
429
drivers/perf/marvell_cn10k_tad_pmu.c
Normal file
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@ -0,0 +1,429 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Marvell CN10K LLC-TAD perf driver
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*
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* Copyright (C) 2021 Marvell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "tad_pmu: " fmt
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/cpuhotplug.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#define TAD_PFC_OFFSET 0x0
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#define TAD_PFC(counter) (TAD_PFC_OFFSET | (counter << 3))
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#define TAD_PRF_OFFSET 0x100
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#define TAD_PRF(counter) (TAD_PRF_OFFSET | (counter << 3))
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#define TAD_PRF_CNTSEL_MASK 0xFF
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#define TAD_MAX_COUNTERS 8
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#define to_tad_pmu(p) (container_of(p, struct tad_pmu, pmu))
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struct tad_region {
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void __iomem *base;
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};
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struct tad_pmu {
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struct pmu pmu;
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struct tad_region *regions;
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u32 region_cnt;
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unsigned int cpu;
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struct hlist_node node;
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struct perf_event *events[TAD_MAX_COUNTERS];
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DECLARE_BITMAP(counters_map, TAD_MAX_COUNTERS);
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};
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static int tad_pmu_cpuhp_state;
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static void tad_pmu_event_counter_read(struct perf_event *event)
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{
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struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u32 counter_idx = hwc->idx;
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u64 prev, new;
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int i;
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do {
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prev = local64_read(&hwc->prev_count);
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for (i = 0, new = 0; i < tad_pmu->region_cnt; i++)
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new += readq(tad_pmu->regions[i].base +
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TAD_PFC(counter_idx));
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} while (local64_cmpxchg(&hwc->prev_count, prev, new) != prev);
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local64_add(new - prev, &event->count);
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}
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static void tad_pmu_event_counter_stop(struct perf_event *event, int flags)
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{
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struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u32 counter_idx = hwc->idx;
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int i;
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/* TAD()_PFC() stop counting on the write
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* which sets TAD()_PRF()[CNTSEL] == 0
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*/
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for (i = 0; i < tad_pmu->region_cnt; i++) {
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writeq_relaxed(0, tad_pmu->regions[i].base +
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TAD_PRF(counter_idx));
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}
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tad_pmu_event_counter_read(event);
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hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
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}
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static void tad_pmu_event_counter_start(struct perf_event *event, int flags)
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{
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struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u32 event_idx = event->attr.config;
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u32 counter_idx = hwc->idx;
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u64 reg_val;
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int i;
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hwc->state = 0;
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/* Typically TAD_PFC() are zeroed to start counting */
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for (i = 0; i < tad_pmu->region_cnt; i++)
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writeq_relaxed(0, tad_pmu->regions[i].base +
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TAD_PFC(counter_idx));
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/* TAD()_PFC() start counting on the write
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* which sets TAD()_PRF()[CNTSEL] != 0
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*/
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for (i = 0; i < tad_pmu->region_cnt; i++) {
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reg_val = readq_relaxed(tad_pmu->regions[i].base +
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TAD_PRF(counter_idx));
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reg_val |= (event_idx & 0xFF);
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writeq_relaxed(reg_val, tad_pmu->regions[i].base +
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TAD_PRF(counter_idx));
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}
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}
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static void tad_pmu_event_counter_del(struct perf_event *event, int flags)
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{
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struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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tad_pmu_event_counter_stop(event, flags | PERF_EF_UPDATE);
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tad_pmu->events[idx] = NULL;
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clear_bit(idx, tad_pmu->counters_map);
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}
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static int tad_pmu_event_counter_add(struct perf_event *event, int flags)
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{
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struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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/* Get a free counter for this event */
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idx = find_first_zero_bit(tad_pmu->counters_map, TAD_MAX_COUNTERS);
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if (idx == TAD_MAX_COUNTERS)
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return -EAGAIN;
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set_bit(idx, tad_pmu->counters_map);
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hwc->idx = idx;
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hwc->state = PERF_HES_STOPPED;
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tad_pmu->events[idx] = event;
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if (flags & PERF_EF_START)
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tad_pmu_event_counter_start(event, flags);
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return 0;
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}
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static int tad_pmu_event_init(struct perf_event *event)
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{
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struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
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if (!event->attr.disabled)
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return -EINVAL;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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if (event->state != PERF_EVENT_STATE_OFF)
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return -EINVAL;
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event->cpu = tad_pmu->cpu;
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event->hw.idx = -1;
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event->hw.config_base = event->attr.config;
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return 0;
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}
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static ssize_t tad_pmu_event_show(struct device *dev,
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struct device_attribute *attr, char *page)
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{
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struct perf_pmu_events_attr *pmu_attr;
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pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
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return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
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}
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#define TAD_PMU_EVENT_ATTR(name, config) \
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PMU_EVENT_ATTR_ID(name, tad_pmu_event_show, config)
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static struct attribute *tad_pmu_event_attrs[] = {
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TAD_PMU_EVENT_ATTR(tad_none, 0x0),
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TAD_PMU_EVENT_ATTR(tad_req_msh_in_any, 0x1),
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TAD_PMU_EVENT_ATTR(tad_req_msh_in_mn, 0x2),
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TAD_PMU_EVENT_ATTR(tad_req_msh_in_exlmn, 0x3),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_any, 0x4),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_mn, 0x5),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_exlmn, 0x6),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_dss, 0x7),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_in_retry_dss, 0x8),
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TAD_PMU_EVENT_ATTR(tad_dat_msh_in_any, 0x9),
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TAD_PMU_EVENT_ATTR(tad_dat_msh_in_dss, 0xa),
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TAD_PMU_EVENT_ATTR(tad_req_msh_out_any, 0xb),
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TAD_PMU_EVENT_ATTR(tad_req_msh_out_dss_rd, 0xc),
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TAD_PMU_EVENT_ATTR(tad_req_msh_out_dss_wr, 0xd),
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TAD_PMU_EVENT_ATTR(tad_req_msh_out_evict, 0xe),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_any, 0xf),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_retry_exlmn, 0x10),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_retry_mn, 0x11),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_exlmn, 0x12),
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TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_mn, 0x13),
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TAD_PMU_EVENT_ATTR(tad_snp_msh_out_any, 0x14),
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TAD_PMU_EVENT_ATTR(tad_snp_msh_out_mn, 0x15),
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TAD_PMU_EVENT_ATTR(tad_snp_msh_out_exlmn, 0x16),
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TAD_PMU_EVENT_ATTR(tad_dat_msh_out_any, 0x17),
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TAD_PMU_EVENT_ATTR(tad_dat_msh_out_fill, 0x18),
|
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TAD_PMU_EVENT_ATTR(tad_dat_msh_out_dss, 0x19),
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TAD_PMU_EVENT_ATTR(tad_alloc_dtg, 0x1a),
|
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TAD_PMU_EVENT_ATTR(tad_alloc_ltg, 0x1b),
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TAD_PMU_EVENT_ATTR(tad_alloc_any, 0x1c),
|
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TAD_PMU_EVENT_ATTR(tad_hit_dtg, 0x1d),
|
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TAD_PMU_EVENT_ATTR(tad_hit_ltg, 0x1e),
|
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TAD_PMU_EVENT_ATTR(tad_hit_any, 0x1f),
|
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TAD_PMU_EVENT_ATTR(tad_tag_rd, 0x20),
|
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TAD_PMU_EVENT_ATTR(tad_dat_rd, 0x21),
|
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TAD_PMU_EVENT_ATTR(tad_dat_rd_byp, 0x22),
|
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TAD_PMU_EVENT_ATTR(tad_ifb_occ, 0x23),
|
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TAD_PMU_EVENT_ATTR(tad_req_occ, 0x24),
|
||||
NULL
|
||||
};
|
||||
|
||||
static const struct attribute_group tad_pmu_events_attr_group = {
|
||||
.name = "events",
|
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.attrs = tad_pmu_event_attrs,
|
||||
};
|
||||
|
||||
PMU_FORMAT_ATTR(event, "config:0-7");
|
||||
|
||||
static struct attribute *tad_pmu_format_attrs[] = {
|
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&format_attr_event.attr,
|
||||
NULL
|
||||
};
|
||||
|
||||
static struct attribute_group tad_pmu_format_attr_group = {
|
||||
.name = "format",
|
||||
.attrs = tad_pmu_format_attrs,
|
||||
};
|
||||
|
||||
static ssize_t tad_pmu_cpumask_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct tad_pmu *tad_pmu = to_tad_pmu(dev_get_drvdata(dev));
|
||||
|
||||
return cpumap_print_to_pagebuf(true, buf, cpumask_of(tad_pmu->cpu));
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(cpumask, 0444, tad_pmu_cpumask_show, NULL);
|
||||
|
||||
static struct attribute *tad_pmu_cpumask_attrs[] = {
|
||||
&dev_attr_cpumask.attr,
|
||||
NULL
|
||||
};
|
||||
|
||||
static struct attribute_group tad_pmu_cpumask_attr_group = {
|
||||
.attrs = tad_pmu_cpumask_attrs,
|
||||
};
|
||||
|
||||
static const struct attribute_group *tad_pmu_attr_groups[] = {
|
||||
&tad_pmu_events_attr_group,
|
||||
&tad_pmu_format_attr_group,
|
||||
&tad_pmu_cpumask_attr_group,
|
||||
NULL
|
||||
};
|
||||
|
||||
static int tad_pmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct tad_region *regions;
|
||||
struct tad_pmu *tad_pmu;
|
||||
struct resource *res;
|
||||
u32 tad_pmu_page_size;
|
||||
u32 tad_page_size;
|
||||
u32 tad_cnt;
|
||||
int i, ret;
|
||||
char *name;
|
||||
|
||||
tad_pmu = devm_kzalloc(&pdev->dev, sizeof(*tad_pmu), GFP_KERNEL);
|
||||
if (!tad_pmu)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, tad_pmu);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "Mem resource not found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(node, "marvell,tad-page-size",
|
||||
&tad_page_size);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't find tad-page-size property\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(node, "marvell,tad-pmu-page-size",
|
||||
&tad_pmu_page_size);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't find tad-pmu-page-size property\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(node, "marvell,tad-cnt", &tad_cnt);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't find tad-cnt property\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
regions = devm_kcalloc(&pdev->dev, tad_cnt,
|
||||
sizeof(*regions), GFP_KERNEL);
|
||||
if (!regions)
|
||||
return -ENOMEM;
|
||||
|
||||
/* ioremap the distributed TAD pmu regions */
|
||||
for (i = 0; i < tad_cnt && res->start < res->end; i++) {
|
||||
regions[i].base = devm_ioremap(&pdev->dev,
|
||||
res->start,
|
||||
tad_pmu_page_size);
|
||||
if (IS_ERR(regions[i].base)) {
|
||||
dev_err(&pdev->dev, "TAD%d ioremap fail\n", i);
|
||||
return -ENOMEM;
|
||||
}
|
||||
res->start += tad_page_size;
|
||||
}
|
||||
|
||||
tad_pmu->regions = regions;
|
||||
tad_pmu->region_cnt = tad_cnt;
|
||||
|
||||
tad_pmu->pmu = (struct pmu) {
|
||||
|
||||
.module = THIS_MODULE,
|
||||
.attr_groups = tad_pmu_attr_groups,
|
||||
.capabilities = PERF_PMU_CAP_NO_EXCLUDE |
|
||||
PERF_PMU_CAP_NO_INTERRUPT,
|
||||
.task_ctx_nr = perf_invalid_context,
|
||||
|
||||
.event_init = tad_pmu_event_init,
|
||||
.add = tad_pmu_event_counter_add,
|
||||
.del = tad_pmu_event_counter_del,
|
||||
.start = tad_pmu_event_counter_start,
|
||||
.stop = tad_pmu_event_counter_stop,
|
||||
.read = tad_pmu_event_counter_read,
|
||||
};
|
||||
|
||||
tad_pmu->cpu = raw_smp_processor_id();
|
||||
|
||||
/* Register pmu instance for cpu hotplug */
|
||||
ret = cpuhp_state_add_instance_nocalls(tad_pmu_cpuhp_state,
|
||||
&tad_pmu->node);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
name = "tad";
|
||||
ret = perf_pmu_register(&tad_pmu->pmu, name, -1);
|
||||
if (ret)
|
||||
cpuhp_state_remove_instance_nocalls(tad_pmu_cpuhp_state,
|
||||
&tad_pmu->node);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tad_pmu_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tad_pmu *pmu = platform_get_drvdata(pdev);
|
||||
|
||||
cpuhp_state_remove_instance_nocalls(tad_pmu_cpuhp_state,
|
||||
&pmu->node);
|
||||
perf_pmu_unregister(&pmu->pmu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id tad_pmu_of_match[] = {
|
||||
{ .compatible = "marvell,cn10k-tad-pmu", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver tad_pmu_driver = {
|
||||
.driver = {
|
||||
.name = "cn10k_tad_pmu",
|
||||
.of_match_table = of_match_ptr(tad_pmu_of_match),
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = tad_pmu_probe,
|
||||
.remove = tad_pmu_remove,
|
||||
};
|
||||
|
||||
static int tad_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
|
||||
{
|
||||
struct tad_pmu *pmu = hlist_entry_safe(node, struct tad_pmu, node);
|
||||
unsigned int target;
|
||||
|
||||
if (cpu != pmu->cpu)
|
||||
return 0;
|
||||
|
||||
target = cpumask_any_but(cpu_online_mask, cpu);
|
||||
if (target >= nr_cpu_ids)
|
||||
return 0;
|
||||
|
||||
perf_pmu_migrate_context(&pmu->pmu, cpu, target);
|
||||
pmu->cpu = target;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init tad_pmu_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
|
||||
"perf/cn10k/tadpmu:online",
|
||||
NULL,
|
||||
tad_pmu_offline_cpu);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
tad_pmu_cpuhp_state = ret;
|
||||
return platform_driver_register(&tad_pmu_driver);
|
||||
}
|
||||
|
||||
static void __exit tad_pmu_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tad_pmu_driver);
|
||||
cpuhp_remove_multi_state(tad_pmu_cpuhp_state);
|
||||
}
|
||||
|
||||
module_init(tad_pmu_init);
|
||||
module_exit(tad_pmu_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Marvell CN10K LLC-TAD Perf driver");
|
||||
MODULE_AUTHOR("Bhaskara Budiredla <bbudiredla@marvell.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user