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arm64: dts: marvell: mcbin: enable the fourth network interface
This patch enables the fourth network interface on the Marvell Macchiatobin. It is configured in the 2500Base-X PHY mode. The SFP cage is also described. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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@ -27,6 +27,7 @@
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp1_eth0;
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ethernet2 = &cp1_eth1;
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ethernet3 = &cp1_eth2;
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};
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/* Regulator labels correspond with schematics */
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@ -88,6 +89,18 @@
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
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};
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sfp_eth3: sfp-eth3 {
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/* CON3,4 - CPS lane 5 */
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compatible = "sff,sfp";
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i2c-bus = <&sfp_1g_i2c>;
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los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
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};
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};
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&uart0 {
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@ -195,6 +208,10 @@
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marvell,pins = "mpp47";
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marvell,function = "gpio";
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};
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cp0_sfp_1g_pins: sfp-1g-pins {
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marvell,pins = "mpp51", "mpp53", "mpp54";
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marvell,function = "gpio";
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};
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cp0_pcie_pins: pcie-pins {
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marvell,pins = "mpp52";
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marvell,function = "gpio";
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@ -287,6 +304,17 @@
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phys = <&cp1_comphy0 1>;
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};
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&cp1_eth2 {
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/* CPS Lane 5 */
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status = "okay";
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/* Network PHY */
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phy-mode = "2500base-x";
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managed = "in-band-status";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp1_comphy5 2>;
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sfp = <&sfp_eth3>;
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};
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&cp1_pinctrl {
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cp1_sfpp1_pins: sfpp1-pins {
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marvell,pins = "mpp8", "mpp10", "mpp11";
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@ -300,6 +328,10 @@
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marvell,pins = "mpp6", "mpp7";
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marvell,function = "uart0";
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};
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cp1_sfp_1g_pins: sfp-1g-pins {
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marvell,pins = "mpp24";
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marvell,function = "gpio";
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};
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cp1_sfpp0_pins: sfpp0-pins {
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marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
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marvell,function = "gpio";
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