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net: stmmac: dwc-qos: Add Tegra186 support
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP core. The binding that it uses is slightly different from existing ones because of the integration (clocks, resets, ...). Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Thierry Reding
David S. Miller
parent
cee45b2eda
commit
e6ea2d16fc
@ -14,17 +14,34 @@
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/ethtool.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/stmmac.h>
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#include "stmmac_platform.h"
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#include "dwmac4.h"
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struct tegra_eqos {
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struct device *dev;
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void __iomem *regs;
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struct reset_control *rst;
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struct clk *clk_master;
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struct clk *clk_slave;
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struct clk *clk_tx;
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struct clk *clk_rx;
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struct gpio_desc *reset;
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};
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static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
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struct plat_stmmacenet_data *plat_dat)
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@ -158,6 +175,230 @@ static int dwc_qos_remove(struct platform_device *pdev)
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return 0;
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}
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#define SDMEMCOMPPADCTRL 0x8800
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#define SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
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#define AUTO_CAL_CONFIG 0x8804
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#define AUTO_CAL_CONFIG_START BIT(31)
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#define AUTO_CAL_CONFIG_ENABLE BIT(29)
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#define AUTO_CAL_STATUS 0x880c
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#define AUTO_CAL_STATUS_ACTIVE BIT(31)
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static void tegra_eqos_fix_speed(void *priv, unsigned int speed)
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{
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struct tegra_eqos *eqos = priv;
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unsigned long rate = 125000000;
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bool needs_calibration = false;
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u32 value;
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int err;
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switch (speed) {
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case SPEED_1000:
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needs_calibration = true;
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rate = 125000000;
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break;
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case SPEED_100:
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needs_calibration = true;
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rate = 25000000;
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break;
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case SPEED_10:
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rate = 2500000;
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break;
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default:
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dev_err(eqos->dev, "invalid speed %u\n", speed);
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break;
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}
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if (needs_calibration) {
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/* calibrate */
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value = readl(eqos->regs + SDMEMCOMPPADCTRL);
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value |= SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD;
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writel(value, eqos->regs + SDMEMCOMPPADCTRL);
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udelay(1);
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value = readl(eqos->regs + AUTO_CAL_CONFIG);
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value |= AUTO_CAL_CONFIG_START | AUTO_CAL_CONFIG_ENABLE;
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writel(value, eqos->regs + AUTO_CAL_CONFIG);
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err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS,
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value,
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value & AUTO_CAL_STATUS_ACTIVE,
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1, 10);
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if (err < 0) {
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dev_err(eqos->dev, "calibration did not start\n");
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goto failed;
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}
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err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS,
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value,
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(value & AUTO_CAL_STATUS_ACTIVE) == 0,
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20, 200);
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if (err < 0) {
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dev_err(eqos->dev, "calibration didn't finish\n");
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goto failed;
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}
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failed:
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value = readl(eqos->regs + SDMEMCOMPPADCTRL);
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value &= ~SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD;
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writel(value, eqos->regs + SDMEMCOMPPADCTRL);
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} else {
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value = readl(eqos->regs + AUTO_CAL_CONFIG);
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value &= ~AUTO_CAL_CONFIG_ENABLE;
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writel(value, eqos->regs + AUTO_CAL_CONFIG);
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}
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err = clk_set_rate(eqos->clk_tx, rate);
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if (err < 0)
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dev_err(eqos->dev, "failed to set TX rate: %d\n", err);
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}
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static int tegra_eqos_init(struct platform_device *pdev, void *priv)
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{
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struct tegra_eqos *eqos = priv;
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unsigned long rate;
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u32 value;
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rate = clk_get_rate(eqos->clk_slave);
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value = (rate / 1000000) - 1;
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writel(value, eqos->regs + GMAC_1US_TIC_COUNTER);
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return 0;
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}
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static void *tegra_eqos_probe(struct platform_device *pdev,
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struct plat_stmmacenet_data *data,
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struct stmmac_resources *res)
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{
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struct tegra_eqos *eqos;
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int err;
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eqos = devm_kzalloc(&pdev->dev, sizeof(*eqos), GFP_KERNEL);
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if (!eqos) {
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err = -ENOMEM;
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goto error;
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}
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eqos->dev = &pdev->dev;
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eqos->regs = res->addr;
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eqos->clk_master = devm_clk_get(&pdev->dev, "master_bus");
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if (IS_ERR(eqos->clk_master)) {
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err = PTR_ERR(eqos->clk_master);
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goto error;
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}
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err = clk_prepare_enable(eqos->clk_master);
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if (err < 0)
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goto error;
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eqos->clk_slave = devm_clk_get(&pdev->dev, "slave_bus");
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if (IS_ERR(eqos->clk_slave)) {
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err = PTR_ERR(eqos->clk_slave);
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goto disable_master;
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}
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data->stmmac_clk = eqos->clk_slave;
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err = clk_prepare_enable(eqos->clk_slave);
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if (err < 0)
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goto disable_master;
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eqos->clk_rx = devm_clk_get(&pdev->dev, "rx");
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if (IS_ERR(eqos->clk_rx)) {
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err = PTR_ERR(eqos->clk_rx);
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goto disable_slave;
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}
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err = clk_prepare_enable(eqos->clk_rx);
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if (err < 0)
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goto disable_slave;
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eqos->clk_tx = devm_clk_get(&pdev->dev, "tx");
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if (IS_ERR(eqos->clk_tx)) {
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err = PTR_ERR(eqos->clk_tx);
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goto disable_rx;
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}
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err = clk_prepare_enable(eqos->clk_tx);
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if (err < 0)
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goto disable_rx;
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eqos->reset = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_OUT_HIGH);
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if (IS_ERR(eqos->reset)) {
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err = PTR_ERR(eqos->reset);
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goto disable_tx;
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}
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usleep_range(2000, 4000);
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gpiod_set_value(eqos->reset, 0);
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eqos->rst = devm_reset_control_get(&pdev->dev, "eqos");
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if (IS_ERR(eqos->rst)) {
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err = PTR_ERR(eqos->rst);
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goto reset_phy;
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}
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err = reset_control_assert(eqos->rst);
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if (err < 0)
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goto reset_phy;
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usleep_range(2000, 4000);
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err = reset_control_deassert(eqos->rst);
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if (err < 0)
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goto reset_phy;
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usleep_range(2000, 4000);
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data->fix_mac_speed = tegra_eqos_fix_speed;
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data->init = tegra_eqos_init;
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data->bsp_priv = eqos;
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err = tegra_eqos_init(pdev, eqos);
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if (err < 0)
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goto reset;
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out:
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return eqos;
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reset:
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reset_control_assert(eqos->rst);
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reset_phy:
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gpiod_set_value(eqos->reset, 1);
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disable_tx:
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clk_disable_unprepare(eqos->clk_tx);
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disable_rx:
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clk_disable_unprepare(eqos->clk_rx);
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disable_slave:
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clk_disable_unprepare(eqos->clk_slave);
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disable_master:
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clk_disable_unprepare(eqos->clk_master);
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error:
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eqos = ERR_PTR(err);
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goto out;
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}
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static int tegra_eqos_remove(struct platform_device *pdev)
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{
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struct tegra_eqos *eqos = get_stmmac_bsp_priv(&pdev->dev);
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reset_control_assert(eqos->rst);
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gpiod_set_value(eqos->reset, 1);
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clk_disable_unprepare(eqos->clk_tx);
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clk_disable_unprepare(eqos->clk_rx);
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clk_disable_unprepare(eqos->clk_slave);
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clk_disable_unprepare(eqos->clk_master);
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return 0;
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}
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struct dwc_eth_dwmac_data {
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void *(*probe)(struct platform_device *pdev,
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struct plat_stmmacenet_data *data,
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@ -170,6 +411,11 @@ static const struct dwc_eth_dwmac_data dwc_qos_data = {
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.remove = dwc_qos_remove,
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};
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static const struct dwc_eth_dwmac_data tegra_eqos_data = {
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.probe = tegra_eqos_probe,
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.remove = tegra_eqos_remove,
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};
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static int dwc_eth_dwmac_probe(struct platform_device *pdev)
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{
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const struct dwc_eth_dwmac_data *data;
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@ -255,6 +501,7 @@ static int dwc_eth_dwmac_remove(struct platform_device *pdev)
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static const struct of_device_id dwc_eth_dwmac_match[] = {
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{ .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
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{ .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data },
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{ }
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};
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MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
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@ -25,6 +25,7 @@
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#define GMAC_RXQ_CTRL0 0x000000a0
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#define GMAC_INT_STATUS 0x000000b0
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#define GMAC_INT_EN 0x000000b4
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#define GMAC_1US_TIC_COUNTER 0x000000dc
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#define GMAC_PCS_BASE 0x000000e0
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#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
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#define GMAC_PMT 0x000000c0
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