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powerpc/perf: Sample only if SIAR-Valid bit is set in P7+
powerpc/perf: Sample only if SIAR-Valid bit is set in P7+ On POWER7+ two new bits (mmcra[35] and mmcra[36]) indicate whether the contents of SIAR and SDAR are valid. For marked instructions on P7+, we must save the contents of SIAR and SDAR registers only if these new bits are set. This code/check for the SIAR-Valid bit is specific to P7+, so rather than waste a CPU-feature bit use the PVR flag. Note that Carl Love proposed a similar change for oprofile: https://lkml.org/lkml/2012/6/22/309 Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -49,6 +49,7 @@ struct power_pmu {
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#define PPMU_ALT_SIPR 2 /* uses alternate posn for SIPR/HV */
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#define PPMU_NO_SIPR 4 /* no SIPR/HV in MMCRA at all */
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#define PPMU_NO_CONT_SAMPLING 8 /* no continuous sampling */
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#define PPMU_SIAR_VALID 16 /* Processor has SIAR Valid bit */
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/*
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* Values for flags to get_alternatives()
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@ -606,6 +606,10 @@
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#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
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#define POWER6_MMCRA_THRM 0x00000020UL
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#define POWER6_MMCRA_OTHER 0x0000000EUL
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#define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */
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#define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */
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#define SPRN_PMC1 787
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#define SPRN_PMC2 788
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#define SPRN_PMC3 789
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@ -82,6 +82,11 @@ static inline int perf_intr_is_nmi(struct pt_regs *regs)
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return 0;
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}
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static inline int siar_valid(struct pt_regs *regs)
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{
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return 1;
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}
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#endif /* CONFIG_PPC32 */
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/*
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@ -106,14 +111,20 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
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* If we're not doing instruction sampling, give them the SDAR
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* (sampled data address). If we are doing instruction sampling, then
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* only give them the SDAR if it corresponds to the instruction
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* pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC
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* bit in MMCRA.
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* pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or
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* the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA.
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*/
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static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
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{
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unsigned long mmcra = regs->dsisr;
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unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
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POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
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unsigned long sdsync;
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if (ppmu->flags & PPMU_SIAR_VALID)
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sdsync = POWER7P_MMCRA_SDAR_VALID;
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else if (ppmu->flags & PPMU_ALT_SIPR)
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sdsync = POWER6_MMCRA_SDSYNC;
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else
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sdsync = MMCRA_SDSYNC;
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if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
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*addrp = mfspr(SPRN_SDAR);
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@ -230,6 +241,24 @@ static inline int perf_intr_is_nmi(struct pt_regs *regs)
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return !regs->softe;
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}
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/*
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* On processors like P7+ that have the SIAR-Valid bit, marked instructions
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* must be sampled only if the SIAR-valid bit is set.
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*
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* For unmarked instructions and for processors that don't have the SIAR-Valid
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* bit, assume that SIAR is valid.
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*/
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static inline int siar_valid(struct pt_regs *regs)
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{
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unsigned long mmcra = regs->dsisr;
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int marked = mmcra & MMCRA_SAMPLE_ENABLE;
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if ((ppmu->flags & PPMU_SIAR_VALID) && marked)
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return mmcra & POWER7P_MMCRA_SIAR_VALID;
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return 1;
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}
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#endif /* CONFIG_PPC64 */
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static void perf_event_interrupt(struct pt_regs *regs);
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@ -1291,6 +1320,7 @@ struct pmu power_pmu = {
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.event_idx = power_pmu_event_idx,
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};
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/*
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* A counter has overflowed; update its count and record
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* things if requested. Note that interrupts are hard-disabled
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@ -1324,7 +1354,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
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left += period;
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if (left <= 0)
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left = period;
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record = 1;
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record = siar_valid(regs);
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event->hw.last_period = event->hw.sample_period;
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}
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if (left < 0x80000000LL)
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@ -1374,8 +1404,10 @@ unsigned long perf_instruction_pointer(struct pt_regs *regs)
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{
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unsigned long use_siar = regs->result;
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if (use_siar)
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if (use_siar && siar_valid(regs))
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return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
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else if (use_siar)
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return 0; // no valid instruction pointer
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else
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return regs->nip;
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}
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@ -373,6 +373,9 @@ static int __init init_power7_pmu(void)
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strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
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return -ENODEV;
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if (pvr_version_is(PVR_POWER7p))
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power7_pmu.flags |= PPMU_SIAR_VALID;
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return register_power_pmu(&power7_pmu);
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}
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