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soc: mediatek: pm-domains: Add support for mt8188
Add domain control data including bus protection data size change due to more protection steps in mt8188. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221223080553.9397-3-Garmin.Chang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Garmin.Chang
Matthias Brugger
parent
1725dde87f
commit
e610e81464
623
drivers/soc/mediatek/mt8188-pm-domains.h
Normal file
623
drivers/soc/mediatek/mt8188-pm-domains.h
Normal file
@ -0,0 +1,623 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <garmin.chang@mediatek.com>
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*/
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#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mediatek,mt8188-power.h>
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/*
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* MT8188 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
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[MT8188_POWER_DOMAIN_MFG0] = {
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.name = "mfg0",
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.sta_mask = BIT(1),
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.ctl_offs = 0x300,
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.pwr_sta_offs = 0x174,
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.pwr_sta2nd_offs = 0x178,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
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},
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[MT8188_POWER_DOMAIN_MFG1] = {
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.name = "mfg1",
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.sta_mask = BIT(2),
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.ctl_offs = 0x304,
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.pwr_sta_offs = 0x174,
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.pwr_sta2nd_offs = 0x178,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
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MT8188_TOP_AXI_PROT_EN_SET,
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MT8188_TOP_AXI_PROT_EN_CLR,
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MT8188_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
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MT8188_TOP_AXI_PROT_EN_1_SET,
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MT8188_TOP_AXI_PROT_EN_1_CLR,
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MT8188_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
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MT8188_TOP_AXI_PROT_EN_SET,
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MT8188_TOP_AXI_PROT_EN_CLR,
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MT8188_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
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},
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[MT8188_POWER_DOMAIN_MFG2] = {
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.name = "mfg2",
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.sta_mask = BIT(3),
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.ctl_offs = 0x308,
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.pwr_sta_offs = 0x174,
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.pwr_sta2nd_offs = 0x178,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8188_POWER_DOMAIN_MFG3] = {
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.name = "mfg3",
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.sta_mask = BIT(4),
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.ctl_offs = 0x30C,
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.pwr_sta_offs = 0x174,
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.pwr_sta2nd_offs = 0x178,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8188_POWER_DOMAIN_MFG4] = {
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.name = "mfg4",
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.sta_mask = BIT(5),
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.ctl_offs = 0x310,
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.pwr_sta_offs = 0x174,
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.pwr_sta2nd_offs = 0x178,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = {
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.name = "pextp_mac_p0",
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.sta_mask = BIT(10),
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.ctl_offs = 0x324,
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.pwr_sta_offs = 0x174,
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.pwr_sta2nd_offs = 0x178,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
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MT8188_TOP_AXI_PROT_EN_SET,
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MT8188_TOP_AXI_PROT_EN_CLR,
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MT8188_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = {
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.name = "pextp_phy_top",
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.sta_mask = BIT(12),
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.ctl_offs = 0x328,
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.pwr_sta_offs = 0x174,
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.pwr_sta2nd_offs = 0x178,
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8188_POWER_DOMAIN_CSIRX_TOP] = {
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.name = "pextp_csirx_top",
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.sta_mask = BIT(17),
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.ctl_offs = 0x3C4,
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.pwr_sta_offs = 0x174,
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.pwr_sta2nd_offs = 0x178,
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8188_POWER_DOMAIN_ETHER] = {
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.name = "ether",
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.sta_mask = BIT(1),
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.ctl_offs = 0x338,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8188_POWER_DOMAIN_HDMI_TX] = {
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.name = "hdmi_tx",
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.sta_mask = BIT(18),
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.ctl_offs = 0x37C,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
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MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8188_POWER_DOMAIN_ADSP_AO] = {
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.name = "adsp_ao",
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.sta_mask = BIT(10),
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.ctl_offs = 0x35C,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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},
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.caps = MTK_SCPD_ALWAYS_ON,
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},
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[MT8188_POWER_DOMAIN_ADSP_INFRA] = {
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.name = "adsp_infra",
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.sta_mask = BIT(9),
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.ctl_offs = 0x358,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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},
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.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON,
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},
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[MT8188_POWER_DOMAIN_ADSP] = {
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.name = "adsp",
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.sta_mask = BIT(8),
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.ctl_offs = 0x354,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8188_POWER_DOMAIN_AUDIO] = {
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.name = "audio",
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.sta_mask = BIT(6),
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.ctl_offs = 0x34C,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8188_POWER_DOMAIN_AUDIO_ASRC] = {
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.name = "audio_asrc",
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.sta_mask = BIT(7),
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.ctl_offs = 0x350,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
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MT8188_TOP_AXI_PROT_EN_2_SET,
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MT8188_TOP_AXI_PROT_EN_2_CLR,
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MT8188_TOP_AXI_PROT_EN_2_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8188_POWER_DOMAIN_VPPSYS0] = {
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.name = "vppsys0",
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.sta_mask = BIT(11),
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.ctl_offs = 0x360,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
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MT8188_TOP_AXI_PROT_EN_SET,
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MT8188_TOP_AXI_PROT_EN_CLR,
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MT8188_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
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MT8188_TOP_AXI_PROT_EN_MM_2_SET,
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MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
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MT8188_TOP_AXI_PROT_EN_MM_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
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MT8188_TOP_AXI_PROT_EN_SET,
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MT8188_TOP_AXI_PROT_EN_CLR,
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MT8188_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
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MT8188_TOP_AXI_PROT_EN_MM_2_SET,
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MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
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MT8188_TOP_AXI_PROT_EN_MM_2_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
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},
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},
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[MT8188_POWER_DOMAIN_VDOSYS0] = {
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.name = "vdosys0",
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.sta_mask = BIT(13),
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.ctl_offs = 0x368,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
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MT8188_TOP_AXI_PROT_EN_MM_SET,
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MT8188_TOP_AXI_PROT_EN_MM_CLR,
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MT8188_TOP_AXI_PROT_EN_MM_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
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MT8188_TOP_AXI_PROT_EN_SET,
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MT8188_TOP_AXI_PROT_EN_CLR,
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MT8188_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
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MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
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},
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},
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[MT8188_POWER_DOMAIN_VDOSYS1] = {
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.name = "vdosys1",
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.sta_mask = BIT(14),
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.ctl_offs = 0x36C,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
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MT8188_TOP_AXI_PROT_EN_MM_SET,
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MT8188_TOP_AXI_PROT_EN_MM_CLR,
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MT8188_TOP_AXI_PROT_EN_MM_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
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MT8188_TOP_AXI_PROT_EN_MM_SET,
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MT8188_TOP_AXI_PROT_EN_MM_CLR,
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MT8188_TOP_AXI_PROT_EN_MM_STA),
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BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
},
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_DP_TX] = {
|
||||
.name = "dp_tx",
|
||||
.sta_mask = BIT(16),
|
||||
.ctl_offs = 0x374,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_EDP_TX] = {
|
||||
.name = "edp_tx",
|
||||
.sta_mask = BIT(17),
|
||||
.ctl_offs = 0x378,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_VPPSYS1] = {
|
||||
.name = "vppsys1",
|
||||
.sta_mask = BIT(12),
|
||||
.ctl_offs = 0x364,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
},
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_WPE] = {
|
||||
.name = "wpe",
|
||||
.sta_mask = BIT(15),
|
||||
.ctl_offs = 0x370,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_VDEC0] = {
|
||||
.name = "vdec0",
|
||||
.sta_mask = BIT(19),
|
||||
.ctl_offs = 0x380,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_VDEC1] = {
|
||||
.name = "vdec1",
|
||||
.sta_mask = BIT(20),
|
||||
.ctl_offs = 0x384,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_VENC] = {
|
||||
.name = "venc",
|
||||
.sta_mask = BIT(22),
|
||||
.ctl_offs = 0x38C,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_IMG_VCORE] = {
|
||||
.name = "vcore",
|
||||
.sta_mask = BIT(28),
|
||||
.ctl_offs = 0x3A4,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_IMG_MAIN] = {
|
||||
.name = "img_main",
|
||||
.sta_mask = BIT(29),
|
||||
.ctl_offs = 0x3A8,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_DIP] = {
|
||||
.name = "dip",
|
||||
.sta_mask = BIT(30),
|
||||
.ctl_offs = 0x3AC,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_IPE] = {
|
||||
.name = "ipe",
|
||||
.sta_mask = BIT(31),
|
||||
.ctl_offs = 0x3B0,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_CAM_VCORE] = {
|
||||
.name = "cam_vcore",
|
||||
.sta_mask = BIT(27),
|
||||
.ctl_offs = 0x3A0,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_2_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
|
||||
MT8188_TOP_AXI_PROT_EN_1_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_1_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_1_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_CAM_MAIN] = {
|
||||
.name = "cam_main",
|
||||
.sta_mask = BIT(24),
|
||||
.ctl_offs = 0x394,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.bp_infracfg = {
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
|
||||
MT8188_TOP_AXI_PROT_EN_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_2_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
|
||||
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
|
||||
MT8188_TOP_AXI_PROT_EN_2_SET,
|
||||
MT8188_TOP_AXI_PROT_EN_2_CLR,
|
||||
MT8188_TOP_AXI_PROT_EN_2_STA),
|
||||
},
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_CAM_SUBA] = {
|
||||
.name = "cam_suba",
|
||||
.sta_mask = BIT(25),
|
||||
.ctl_offs = 0x398,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
[MT8188_POWER_DOMAIN_CAM_SUBB] = {
|
||||
.name = "cam_subb",
|
||||
.sta_mask = BIT(26),
|
||||
.ctl_offs = 0x39C,
|
||||
.pwr_sta_offs = 0x16C,
|
||||
.pwr_sta2nd_offs = 0x170,
|
||||
.sram_pdn_bits = BIT(8),
|
||||
.sram_pdn_ack_bits = BIT(12),
|
||||
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct scpsys_soc_data mt8188_scpsys_data = {
|
||||
.domains_data = scpsys_domain_data_mt8188,
|
||||
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188),
|
||||
};
|
||||
|
||||
#endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */
|
||||
@ -21,6 +21,7 @@
|
||||
#include "mt8173-pm-domains.h"
|
||||
#include "mt8183-pm-domains.h"
|
||||
#include "mt8186-pm-domains.h"
|
||||
#include "mt8188-pm-domains.h"
|
||||
#include "mt8192-pm-domains.h"
|
||||
#include "mt8195-pm-domains.h"
|
||||
|
||||
@ -579,6 +580,10 @@ static const struct of_device_id scpsys_of_match[] = {
|
||||
.compatible = "mediatek,mt8186-power-controller",
|
||||
.data = &mt8186_scpsys_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8188-power-controller",
|
||||
.data = &mt8188_scpsys_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8192-power-controller",
|
||||
.data = &mt8192_scpsys_data,
|
||||
|
||||
@ -140,6 +140,127 @@
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
|
||||
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_SET 0x2A0
|
||||
#define MT8188_TOP_AXI_PROT_EN_CLR 0x2A4
|
||||
#define MT8188_TOP_AXI_PROT_EN_STA 0x228
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_SET 0x2A8
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_CLR 0x2AC
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_STA 0x258
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_SET 0x714
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_CLR 0x718
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_STA 0x724
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_SET 0x2D4
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_CLR 0x2D8
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_STA 0x2EC
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_SET 0xDCC
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR 0xDD0
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_STA 0xDD8
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET 0xB84
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR 0xB88
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA 0xB90
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xBCC
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xBD0
|
||||
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA 0xBD8
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1 BIT(11)
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#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2 BIT(7)
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#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3 BIT(19)
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#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(5)
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#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 GENMASK(22, 21)
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#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6 BIT(17)
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#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1 BIT(2)
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#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8) | BIT(18) | BIT(30))
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#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1 BIT(24)
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#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1 BIT(20)
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#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1 GENMASK(31, 29)
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#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2 (GENMASK(4, 3) | BIT(28))
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#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMASK(16, 14) | BIT(23) | \
|
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BIT(27))
|
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#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25))
|
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#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 GENMASK(11, 8)
|
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#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 GENMASK(22, 21)
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#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1 BIT(20)
|
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#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2 BIT(12)
|
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#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1 BIT(24)
|
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#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2 BIT(13)
|
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|
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#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1 BIT(10)
|
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#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 GENMASK(9, 8)
|
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#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3 BIT(23)
|
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#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1) | BIT(4) | BIT(11))
|
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#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5 (BIT(20))
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20))
|
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#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2 BIT(6)
|
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#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3 BIT(21)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1 GENMASK(31, 30)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2 BIT(22)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3 BIT(10)
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1 BIT(23)
|
||||
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1 BIT(22)
|
||||
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1 GENMASK(6, 5)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2 BIT(23)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3 BIT(18)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1 BIT(23)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2 BIT(21)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(13)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(13)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(14)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(29)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1 (BIT(9) | BIT(11))
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2 BIT(26)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3 BIT(2)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1 (BIT(1) | BIT(3))
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2 BIT(25)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3 BIT(16)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 GENMASK(27, 26)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 GENMASK(25, 24)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1 (BIT(2) | BIT(4))
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 BIT(0)
|
||||
#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3 BIT(22)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4 BIT(24)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5 BIT(17)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 GENMASK(31, 30)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2 BIT(2)
|
||||
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 GENMASK(29, 28)
|
||||
#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4 BIT(1)
|
||||
|
||||
#define MT8188_SMI_COMMON_CLAMP_EN_STA 0x3C0
|
||||
#define MT8188_SMI_COMMON_CLAMP_EN_SET 0x3C4
|
||||
#define MT8188_SMI_COMMON_CLAMP_EN_CLR 0x3C8
|
||||
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0 GENMASK(3, 1)
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1 GENMASK(2, 1)
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1 BIT(0)
|
||||
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 GENMASK(3, 2)
|
||||
#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 GENMASK(3, 2)
|
||||
|
||||
#define MT8188_SMI_LARB10_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB11A_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB11C_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB12_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB11B_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB15_RESET_ADDR 0xC
|
||||
#define MT8188_SMI_LARB16B_RESET_ADDR 0xA0
|
||||
#define MT8188_SMI_LARB17B_RESET_ADDR 0xA0
|
||||
#define MT8188_SMI_LARB16A_RESET_ADDR 0xA0
|
||||
#define MT8188_SMI_LARB17A_RESET_ADDR 0xA0
|
||||
|
||||
#define MT8188_SMI_LARB10_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB11A_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB11C_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB12_RESET BIT(8)
|
||||
#define MT8188_SMI_LARB11B_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB15_RESET BIT(0)
|
||||
#define MT8188_SMI_LARB16B_RESET BIT(4)
|
||||
#define MT8188_SMI_LARB17B_RESET BIT(4)
|
||||
#define MT8188_SMI_LARB16A_RESET BIT(4)
|
||||
#define MT8188_SMI_LARB17A_RESET BIT(4)
|
||||
|
||||
#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
|
||||
#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
|
||||
#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user