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spi: spi-geni-qcom: Add support for SE DMA mode
SE DMA mode can be used for larger transfers and FIFO mode for smaller transfers. Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/1670509544-15977-1-git-send-email-quic_vnivarth@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vijaya Krishna Nivarthi
Mark Brown
parent
1b929c02af
commit
e5f0dfa78a
@ -87,6 +87,8 @@ struct spi_geni_master {
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struct completion cs_done;
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struct completion cancel_done;
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struct completion abort_done;
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struct completion tx_reset_done;
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struct completion rx_reset_done;
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unsigned int oversampling;
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spinlock_t lock;
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int irq;
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@ -95,6 +97,8 @@ struct spi_geni_master {
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struct dma_chan *tx;
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struct dma_chan *rx;
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int cur_xfer_mode;
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dma_addr_t tx_se_dma;
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dma_addr_t rx_se_dma;
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};
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static int get_spi_clk_cfg(unsigned int speed_hz,
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@ -129,23 +133,27 @@ static int get_spi_clk_cfg(unsigned int speed_hz,
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return ret;
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}
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static void handle_fifo_timeout(struct spi_master *spi,
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static void handle_se_timeout(struct spi_master *spi,
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struct spi_message *msg)
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{
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struct spi_geni_master *mas = spi_master_get_devdata(spi);
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unsigned long time_left;
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struct geni_se *se = &mas->se;
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const struct spi_transfer *xfer;
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spin_lock_irq(&mas->lock);
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reinit_completion(&mas->cancel_done);
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writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
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if (mas->cur_xfer_mode == GENI_SE_FIFO)
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writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
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xfer = mas->cur_xfer;
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mas->cur_xfer = NULL;
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geni_se_cancel_m_cmd(se);
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spin_unlock_irq(&mas->lock);
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time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
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if (time_left)
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return;
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goto unmap_if_dma;
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spin_lock_irq(&mas->lock);
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reinit_completion(&mas->abort_done);
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@ -162,6 +170,39 @@ static void handle_fifo_timeout(struct spi_master *spi,
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*/
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mas->abort_failed = true;
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}
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unmap_if_dma:
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if (mas->cur_xfer_mode == GENI_SE_DMA) {
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if (xfer) {
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if (xfer->tx_buf && mas->tx_se_dma) {
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spin_lock_irq(&mas->lock);
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reinit_completion(&mas->tx_reset_done);
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writel(1, se->base + SE_DMA_TX_FSM_RST);
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spin_unlock_irq(&mas->lock);
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time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ);
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if (!time_left)
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dev_err(mas->dev, "DMA TX RESET failed\n");
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geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len);
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}
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if (xfer->rx_buf && mas->rx_se_dma) {
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spin_lock_irq(&mas->lock);
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reinit_completion(&mas->rx_reset_done);
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writel(1, se->base + SE_DMA_RX_FSM_RST);
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spin_unlock_irq(&mas->lock);
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time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ);
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if (!time_left)
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dev_err(mas->dev, "DMA RX RESET failed\n");
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geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len);
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}
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} else {
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/*
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* This can happen if a timeout happened and we had to wait
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* for lock in this function because isr was holding the lock
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* and handling transfer completion at that time.
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*/
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dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n");
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}
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}
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}
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static void handle_gpi_timeout(struct spi_master *spi, struct spi_message *msg)
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@ -178,7 +219,8 @@ static void spi_geni_handle_err(struct spi_master *spi, struct spi_message *msg)
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switch (mas->cur_xfer_mode) {
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case GENI_SE_FIFO:
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handle_fifo_timeout(spi, msg);
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case GENI_SE_DMA:
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handle_se_timeout(spi, msg);
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break;
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case GENI_GPI_DMA:
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handle_gpi_timeout(spi, msg);
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@ -250,6 +292,8 @@ static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
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}
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mas->cs_flag = set_flag;
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/* set xfer_mode to FIFO to complete cs_done in isr */
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mas->cur_xfer_mode = GENI_SE_FIFO;
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reinit_completion(&mas->cs_done);
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if (set_flag)
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geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
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@ -260,7 +304,7 @@ static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
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time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
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if (!time_left) {
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dev_warn(mas->dev, "Timeout setting chip select\n");
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handle_fifo_timeout(spi, NULL);
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handle_se_timeout(spi, NULL);
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}
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exit:
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@ -482,8 +526,12 @@ static bool geni_can_dma(struct spi_controller *ctlr,
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{
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struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
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/* check if dma is supported */
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return mas->cur_xfer_mode != GENI_SE_FIFO;
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/*
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* Return true if transfer needs to be mapped prior to
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* calling transfer_one which is the case only for GPI_DMA.
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* For SE_DMA mode, map/unmap is done in geni_se_*x_dma_prep.
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*/
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return mas->cur_xfer_mode == GENI_GPI_DMA;
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}
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static int spi_geni_prepare_message(struct spi_master *spi,
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@ -494,6 +542,7 @@ static int spi_geni_prepare_message(struct spi_master *spi,
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switch (mas->cur_xfer_mode) {
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case GENI_SE_FIFO:
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case GENI_SE_DMA:
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if (spi_geni_is_abort_still_pending(mas))
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return -EBUSY;
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ret = setup_fifo_params(spi_msg->spi, spi);
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@ -597,7 +646,7 @@ static int spi_geni_init(struct spi_geni_master *mas)
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break;
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}
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/*
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* in case of failure to get dma channel, we can still do the
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* in case of failure to get gpi dma channel, we can still do the
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* FIFO mode, so fallthrough
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*/
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dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
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@ -716,12 +765,12 @@ static void geni_spi_handle_rx(struct spi_geni_master *mas)
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mas->rx_rem_bytes -= rx_bytes;
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}
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static void setup_fifo_xfer(struct spi_transfer *xfer,
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static int setup_se_xfer(struct spi_transfer *xfer,
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struct spi_geni_master *mas,
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u16 mode, struct spi_master *spi)
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{
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u32 m_cmd = 0;
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u32 len;
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u32 len, fifo_size;
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struct geni_se *se = &mas->se;
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int ret;
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@ -748,7 +797,7 @@ static void setup_fifo_xfer(struct spi_transfer *xfer,
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/* Speed and bits per word can be overridden per transfer */
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ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
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if (ret)
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return;
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return ret;
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mas->tx_rem_bytes = 0;
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mas->rx_rem_bytes = 0;
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@ -772,17 +821,50 @@ static void setup_fifo_xfer(struct spi_transfer *xfer,
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mas->rx_rem_bytes = xfer->len;
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}
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/* Select transfer mode based on transfer length */
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fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word;
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mas->cur_xfer_mode = (len <= fifo_size) ? GENI_SE_FIFO : GENI_SE_DMA;
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geni_se_select_mode(se, mas->cur_xfer_mode);
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/*
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* Lock around right before we start the transfer since our
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* interrupt could come in at any time now.
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*/
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spin_lock_irq(&mas->lock);
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geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
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if (m_cmd & SPI_TX_ONLY) {
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if (mas->cur_xfer_mode == GENI_SE_DMA) {
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if (m_cmd & SPI_RX_ONLY) {
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ret = geni_se_rx_dma_prep(se, xfer->rx_buf,
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xfer->len, &mas->rx_se_dma);
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if (ret) {
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dev_err(mas->dev, "Failed to setup Rx dma %d\n", ret);
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mas->rx_se_dma = 0;
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goto unlock_and_return;
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}
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}
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if (m_cmd & SPI_TX_ONLY) {
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ret = geni_se_tx_dma_prep(se, (void *)xfer->tx_buf,
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xfer->len, &mas->tx_se_dma);
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if (ret) {
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dev_err(mas->dev, "Failed to setup Tx dma %d\n", ret);
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mas->tx_se_dma = 0;
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if (m_cmd & SPI_RX_ONLY) {
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/* Unmap rx buffer if duplex transfer */
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geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len);
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mas->rx_se_dma = 0;
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}
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goto unlock_and_return;
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}
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}
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} else if (m_cmd & SPI_TX_ONLY) {
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if (geni_spi_handle_tx(mas))
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writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
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}
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unlock_and_return:
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spin_unlock_irq(&mas->lock);
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return ret;
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}
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static int spi_geni_transfer_one(struct spi_master *spi,
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@ -790,6 +872,7 @@ static int spi_geni_transfer_one(struct spi_master *spi,
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struct spi_transfer *xfer)
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{
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struct spi_geni_master *mas = spi_master_get_devdata(spi);
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int ret;
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if (spi_geni_is_abort_still_pending(mas))
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return -EBUSY;
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@ -798,9 +881,12 @@ static int spi_geni_transfer_one(struct spi_master *spi,
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if (!xfer->len)
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return 0;
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if (mas->cur_xfer_mode == GENI_SE_FIFO) {
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setup_fifo_xfer(xfer, mas, slv->mode, spi);
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return 1;
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if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) {
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ret = setup_se_xfer(xfer, mas, slv->mode, spi);
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/* SPI framework expects +ve ret code to wait for transfer complete */
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if (!ret)
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ret = 1;
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return ret;
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}
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return setup_gsi_xfer(xfer, mas, slv, spi);
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}
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@ -823,39 +909,70 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
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spin_lock(&mas->lock);
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if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
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geni_spi_handle_rx(mas);
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if (mas->cur_xfer_mode == GENI_SE_FIFO) {
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if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
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geni_spi_handle_rx(mas);
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if (m_irq & M_TX_FIFO_WATERMARK_EN)
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geni_spi_handle_tx(mas);
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if (m_irq & M_TX_FIFO_WATERMARK_EN)
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geni_spi_handle_tx(mas);
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if (m_irq & M_CMD_DONE_EN) {
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if (mas->cur_xfer) {
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if (m_irq & M_CMD_DONE_EN) {
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if (mas->cur_xfer) {
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spi_finalize_current_transfer(spi);
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mas->cur_xfer = NULL;
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/*
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* If this happens, then a CMD_DONE came before all the
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* Tx buffer bytes were sent out. This is unusual, log
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* this condition and disable the WM interrupt to
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* prevent the system from stalling due an interrupt
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* storm.
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*
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* If this happens when all Rx bytes haven't been
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* received, log the condition. The only known time
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* this can happen is if bits_per_word != 8 and some
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* registers that expect xfer lengths in num spi_words
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* weren't written correctly.
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*/
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if (mas->tx_rem_bytes) {
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writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
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dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
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mas->tx_rem_bytes, mas->cur_bits_per_word);
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}
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if (mas->rx_rem_bytes)
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dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
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mas->rx_rem_bytes, mas->cur_bits_per_word);
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} else {
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complete(&mas->cs_done);
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}
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}
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} else if (mas->cur_xfer_mode == GENI_SE_DMA) {
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const struct spi_transfer *xfer = mas->cur_xfer;
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u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);
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u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);
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if (dma_tx_status)
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writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);
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if (dma_rx_status)
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writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR);
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if (dma_tx_status & TX_DMA_DONE)
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mas->tx_rem_bytes = 0;
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if (dma_rx_status & RX_DMA_DONE)
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mas->rx_rem_bytes = 0;
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if (dma_tx_status & TX_RESET_DONE)
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complete(&mas->tx_reset_done);
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if (dma_rx_status & RX_RESET_DONE)
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complete(&mas->rx_reset_done);
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if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) {
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if (xfer->tx_buf && mas->tx_se_dma) {
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geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len);
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mas->tx_se_dma = 0;
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}
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if (xfer->rx_buf && mas->rx_se_dma) {
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geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len);
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mas->rx_se_dma = 0;
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}
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spi_finalize_current_transfer(spi);
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mas->cur_xfer = NULL;
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/*
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* If this happens, then a CMD_DONE came before all the
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* Tx buffer bytes were sent out. This is unusual, log
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* this condition and disable the WM interrupt to
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* prevent the system from stalling due an interrupt
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* storm.
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*
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* If this happens when all Rx bytes haven't been
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* received, log the condition. The only known time
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* this can happen is if bits_per_word != 8 and some
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* registers that expect xfer lengths in num spi_words
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* weren't written correctly.
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*/
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if (mas->tx_rem_bytes) {
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writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
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dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
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mas->tx_rem_bytes, mas->cur_bits_per_word);
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}
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if (mas->rx_rem_bytes)
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dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
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mas->rx_rem_bytes, mas->cur_bits_per_word);
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} else {
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complete(&mas->cs_done);
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}
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}
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@ -949,6 +1066,8 @@ static int spi_geni_probe(struct platform_device *pdev)
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init_completion(&mas->cs_done);
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init_completion(&mas->cancel_done);
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init_completion(&mas->abort_done);
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init_completion(&mas->tx_reset_done);
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init_completion(&mas->rx_reset_done);
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spin_lock_init(&mas->lock);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
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