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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] vmlinux.lds.S: handle .text.* [MIPS] Fix potential latency problem due to non-atomic cpu_wait. [MIPS] SMTC: Clear TIF_FPUBOUND on clone / fork. [MIPS] Fix 64-bit IP checksum code
This commit is contained in:
Linus Torvalds
commit
e59e14b660
@ -45,18 +45,7 @@ static void r39xx_wait(void)
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local_irq_enable();
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}
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/*
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* There is a race when WAIT instruction executed with interrupt
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* enabled.
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* But it is implementation-dependent wheter the pipelie restarts when
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* a non-enabled interrupt is requested.
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*/
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static void r4k_wait(void)
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{
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__asm__(" .set mips3 \n"
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" wait \n"
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" .set mips0 \n");
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}
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extern void r4k_wait(void);
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/*
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* This variant is preferable as it allows testing need_resched and going to
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@ -128,7 +117,7 @@ static int __init wait_disable(char *s)
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__setup("nowait", wait_disable);
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static inline void check_wait(void)
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void __init check_wait(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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@ -242,7 +231,6 @@ static inline void check_errata(void)
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void __init check_bugs32(void)
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{
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check_wait();
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check_errata();
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}
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@ -20,6 +20,7 @@
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#include <asm/stackframe.h>
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#include <asm/war.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#define PANIC_PIC(msg) \
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.set push; \
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@ -126,7 +127,42 @@ handle_vcei:
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__FINIT
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.align 5 /* 32 byte rollback region */
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LEAF(r4k_wait)
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.set push
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.set noreorder
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/* start of rollback region */
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LONG_L t0, TI_FLAGS($28)
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nop
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andi t0, _TIF_NEED_RESCHED
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bnez t0, 1f
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nop
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nop
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nop
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.set mips3
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wait
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/* end of rollback region (the region size must be power of two) */
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.set pop
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1:
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jr ra
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END(r4k_wait)
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.macro BUILD_ROLLBACK_PROLOGUE handler
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FEXPORT(rollback_\handler)
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.set push
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.set noat
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MFC0 k0, CP0_EPC
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PTR_LA k1, r4k_wait
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ori k0, 0x1f /* 32 byte rollback region */
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xori k0, 0x1f
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bne k0, k1, 9f
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MTC0 k0, CP0_EPC
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9:
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.set pop
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.endm
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.align 5
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BUILD_ROLLBACK_PROLOGUE handle_int
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NESTED(handle_int, PT_SIZE, sp)
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#ifdef CONFIG_TRACE_IRQFLAGS
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/*
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@ -201,6 +237,7 @@ NESTED(except_vec_ejtag_debug, 0, sp)
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* This prototype is copied to ebase + n*IntCtl.VS and patched
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* to invoke the handler
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*/
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BUILD_ROLLBACK_PROLOGUE except_vec_vi
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NESTED(except_vec_vi, 0, sp)
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SAVE_SOME
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SAVE_AT
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@ -148,6 +148,8 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
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clear_tsk_thread_flag(p, TIF_USEDFPU);
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#ifdef CONFIG_MIPS_MT_FPAFF
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clear_tsk_thread_flag(p, TIF_FPUBOUND);
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/*
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* FPU affinity support is cleaner if we track the
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* user-visible CPU affinity from the very beginning.
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@ -46,6 +46,9 @@
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#include <asm/types.h>
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#include <asm/stacktrace.h>
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extern void check_wait(void);
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extern asmlinkage void r4k_wait(void);
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extern asmlinkage void rollback_handle_int(void);
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extern asmlinkage void handle_int(void);
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extern asmlinkage void handle_tlbm(void);
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extern asmlinkage void handle_tlbl(void);
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@ -1251,6 +1254,9 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
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extern char except_vec_vi, except_vec_vi_lui;
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extern char except_vec_vi_ori, except_vec_vi_end;
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extern char rollback_except_vec_vi;
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char *vec_start = (cpu_wait == r4k_wait) ?
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&rollback_except_vec_vi : &except_vec_vi;
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* We need to provide the SMTC vectored interrupt handler
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@ -1258,11 +1264,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
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* Status.IM bit to be masked before going there.
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*/
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extern char except_vec_vi_mori;
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const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
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const int mori_offset = &except_vec_vi_mori - vec_start;
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#endif /* CONFIG_MIPS_MT_SMTC */
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const int handler_len = &except_vec_vi_end - &except_vec_vi;
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const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
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const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
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const int handler_len = &except_vec_vi_end - vec_start;
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const int lui_offset = &except_vec_vi_lui - vec_start;
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const int ori_offset = &except_vec_vi_ori - vec_start;
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if (handler_len > VECTORSPACING) {
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/*
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@ -1272,7 +1278,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
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panic("VECTORSPACING too small");
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}
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memcpy(b, &except_vec_vi, handler_len);
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memcpy(b, vec_start, handler_len);
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#ifdef CONFIG_MIPS_MT_SMTC
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BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
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@ -1554,6 +1560,10 @@ void __init trap_init(void)
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extern char except_vec3_generic, except_vec3_r4000;
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extern char except_vec4;
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unsigned long i;
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int rollback;
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check_wait();
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rollback = (cpu_wait == r4k_wait);
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#if defined(CONFIG_KGDB)
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if (kgdb_early_setup)
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@ -1618,7 +1628,7 @@ void __init trap_init(void)
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if (board_be_init)
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board_be_init();
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set_except_vector(0, handle_int);
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set_except_vector(0, rollback ? rollback_handle_int : handle_int);
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set_except_vector(1, handle_tlbm);
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set_except_vector(2, handle_tlbl);
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set_except_vector(3, handle_tlbs);
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@ -36,6 +36,7 @@ SECTIONS
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SCHED_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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*(.text.*)
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*(.fixup)
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*(.gnu.warning)
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} :text = 0
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@ -39,12 +39,14 @@
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#ifdef USE_DOUBLE
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#define LOAD ld
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#define LOAD32 lwu
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#define ADD daddu
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#define NBYTES 8
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#else
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#define LOAD lw
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#define LOAD32 lw
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#define ADD addu
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#define NBYTES 4
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@ -60,6 +62,14 @@
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ADD sum, v1; \
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.set pop
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#define ADDC32(sum,reg) \
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.set push; \
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.set noat; \
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addu sum, reg; \
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sltu v1, sum, reg; \
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addu sum, v1; \
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.set pop
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#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
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LOAD _t0, (offset + UNIT(0))(src); \
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LOAD _t1, (offset + UNIT(1))(src); \
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@ -132,7 +142,7 @@ LEAF(csum_partial)
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beqz t8, .Lqword_align
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andi t8, src, 0x8
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lw t0, 0x00(src)
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LOAD32 t0, 0x00(src)
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LONG_SUBU a1, a1, 0x4
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ADDC(sum, t0)
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PTR_ADDU src, src, 0x4
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@ -211,7 +221,7 @@ LEAF(csum_partial)
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LONG_SRL t8, t8, 0x2
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.Lend_words:
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lw t0, (src)
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LOAD32 t0, (src)
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LONG_SUBU t8, t8, 0x1
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ADDC(sum, t0)
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.set reorder /* DADDI_WAR */
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@ -230,6 +240,9 @@ LEAF(csum_partial)
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/* Still a full word to go */
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ulw t1, (src)
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PTR_ADDIU src, 4
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#ifdef USE_DOUBLE
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dsll t1, t1, 32 /* clear lower 32bit */
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#endif
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ADDC(sum, t1)
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1: move t1, zero
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@ -280,7 +293,7 @@ LEAF(csum_partial)
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1:
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.set reorder
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/* Add the passed partial csum. */
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ADDC(sum, a2)
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ADDC32(sum, a2)
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jr ra
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.set noreorder
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END(csum_partial)
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@ -681,7 +694,7 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
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.set pop
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1:
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.set reorder
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ADDC(sum, psum)
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ADDC32(sum, psum)
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jr ra
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.set noreorder
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