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clk: imx: clk-pllv3: Switch to clk_hw based API
Switch the imx_clk_hw_pllv3 function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -416,14 +416,15 @@ static const struct clk_ops clk_pllv3_enet_ops = {
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.recalc_rate = clk_pllv3_enet_recalc_rate,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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u32 div_mask)
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{
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struct clk_pllv3 *pll;
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const struct clk_ops *ops;
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struct clk *clk;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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@ -484,10 +485,13 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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init.num_parents = 1;
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pll->hw.init = &init;
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hw = &pll->hw;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk))
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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return clk;
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return hw;
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}
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@ -64,6 +64,9 @@ struct imx_pll14xx_clk {
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clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
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cgr_val, clk_gate_flags, lock, share_count)->clk
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#define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
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imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)->clk
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struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
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void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
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@ -96,7 +99,7 @@ enum imx_pllv3_type {
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IMX_PLLV3_AV_IMX7,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base, u32 div_mask);
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struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
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