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KVM: MMU: Do not unconditionally read PDPTE from guest memory
Architecturally, PDPTEs are cached in the PDPTRs when CR3 is reloaded. On SVM, it is not possible to implement this, but on VMX this is possible and was indeed implemented until nested SVM changed this to unconditionally read PDPTEs dynamically. This has noticable impact when running PAE guests. Fix by changing the MMU to read PDPTRs from the cache, falling back to reading from memory for the nested MMU. Signed-off-by: Avi Kivity <avi@redhat.com> Tested-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
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@ -265,6 +265,7 @@ struct kvm_mmu {
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void (*new_cr3)(struct kvm_vcpu *vcpu);
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void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root);
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unsigned long (*get_cr3)(struct kvm_vcpu *vcpu);
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u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
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int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err,
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bool prefault);
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void (*inject_page_fault)(struct kvm_vcpu *vcpu,
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@ -45,13 +45,6 @@ static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index)
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return vcpu->arch.walk_mmu->pdptrs[index];
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}
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static inline u64 kvm_pdptr_read_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, int index)
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{
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load_pdptrs(vcpu, mmu, mmu->get_cr3(vcpu));
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return mmu->pdptrs[index];
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}
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static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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ulong tmask = mask & KVM_POSSIBLE_CR0_GUEST_BITS;
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@ -2770,7 +2770,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
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ASSERT(!VALID_PAGE(root));
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if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
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pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
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pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
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if (!is_present_gpte(pdptr)) {
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vcpu->arch.mmu.pae_root[i] = 0;
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continue;
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@ -3318,6 +3318,7 @@ static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
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context->direct_map = true;
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context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
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context->get_cr3 = get_cr3;
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context->get_pdptr = kvm_pdptr_read;
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context->inject_page_fault = kvm_inject_page_fault;
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context->nx = is_nx(vcpu);
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@ -3376,6 +3377,7 @@ static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
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vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
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vcpu->arch.walk_mmu->get_cr3 = get_cr3;
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vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
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vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
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return r;
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@ -3386,6 +3388,7 @@ static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
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struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
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g_context->get_cr3 = get_cr3;
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g_context->get_pdptr = kvm_pdptr_read;
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g_context->inject_page_fault = kvm_inject_page_fault;
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/*
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@ -163,7 +163,7 @@ retry_walk:
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#if PTTYPE == 64
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if (walker->level == PT32E_ROOT_LEVEL) {
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pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
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pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
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trace_kvm_mmu_paging_element(pte, walker->level);
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if (!is_present_gpte(pte))
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goto error;
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@ -1844,6 +1844,20 @@ static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
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return svm->nested.nested_cr3;
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}
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static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
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{
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struct vcpu_svm *svm = to_svm(vcpu);
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u64 cr3 = svm->nested.nested_cr3;
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u64 pdpte;
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int ret;
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ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
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offset_in_page(cr3) + index * 8, 8);
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if (ret)
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return 0;
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return pdpte;
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}
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static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
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unsigned long root)
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{
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@ -1875,6 +1889,7 @@ static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
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vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
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vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
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vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
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vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
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vcpu->arch.mmu.shadow_root_level = get_npt_level();
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vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
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