ASoC: cs35l56: Add driver for Cirrus Logic CS35L56

The CS35L56 combines a high-performance mono audio amplifier, Class-H
tracking inductive boost converter, Halo Core(TM) DSP and a DC-DC boost
converter supporting Class-H tracking.

Supported control interfaces are I2C, SPI or SoundWire.
Supported audio interfaces are I2S/TDM or SoundWire.

Most chip functionality is controlled by on-board ROM firmware that is
always running. The driver must apply patch/tune to the firmware
before using the CS35L56.

Signed-off-by: Simon Trimmer <simont@opensource.cirrus.com>
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230320112245.115720-9-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>

MAINTAINERS

@@ -4905,6 +4905,7 @@ L:	patches@opensource.cirrus.com
 S:	Maintained
 F:	Documentation/devicetree/bindings/sound/cirrus,cs*
 F:	include/dt-bindings/sound/cs*
+F:	include/sound/cs*
 F:	sound/pci/hda/cs*
 F:	sound/pci/hda/hda_cs_dsp_ctl.*
 F:	sound/soc/codecs/cs*

include/sound/cs35l56.h

@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Common definitions for Cirrus Logic CS35L56 smart amp
+ *
+ * Copyright (C) 2023 Cirrus Logic, Inc. and
+ *                    Cirrus Logic International Semiconductor Ltd.
+ */
+
+#ifndef __CS35L56_H
+#define __CS35L56_H
+
+#include <linux/firmware/cirrus/cs_dsp.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regmap.h>
+
+#define CS35L56_DEVID					0x0000000
+#define CS35L56_REVID					0x0000004
+#define CS35L56_RELID					0x000000C
+#define CS35L56_OTPID					0x0000010
+#define CS35L56_SFT_RESET				0x0000020
+#define CS35L56_GLOBAL_ENABLES				0x0002014
+#define CS35L56_BLOCK_ENABLES				0x0002018
+#define CS35L56_BLOCK_ENABLES2				0x000201C
+#define CS35L56_REFCLK_INPUT				0x0002C04
+#define CS35L56_GLOBAL_SAMPLE_RATE			0x0002C0C
+#define CS35L56_ASP1_ENABLES1				0x0004800
+#define CS35L56_ASP1_CONTROL1				0x0004804
+#define CS35L56_ASP1_CONTROL2				0x0004808
+#define CS35L56_ASP1_CONTROL3				0x000480C
+#define CS35L56_ASP1_FRAME_CONTROL1			0x0004810
+#define CS35L56_ASP1_FRAME_CONTROL5			0x0004820
+#define CS35L56_ASP1_DATA_CONTROL1			0x0004830
+#define CS35L56_ASP1_DATA_CONTROL5			0x0004840
+#define CS35L56_DACPCM1_INPUT				0x0004C00
+#define CS35L56_DACPCM2_INPUT				0x0004C08
+#define CS35L56_ASP1TX1_INPUT				0x0004C20
+#define CS35L56_ASP1TX2_INPUT				0x0004C24
+#define CS35L56_ASP1TX3_INPUT				0x0004C28
+#define CS35L56_ASP1TX4_INPUT				0x0004C2C
+#define CS35L56_DSP1RX1_INPUT				0x0004C40
+#define CS35L56_DSP1RX2_INPUT				0x0004C44
+#define CS35L56_SWIRE_DP3_CH1_INPUT			0x0004C70
+#define CS35L56_SWIRE_DP3_CH2_INPUT			0x0004C74
+#define CS35L56_SWIRE_DP3_CH3_INPUT			0x0004C78
+#define CS35L56_SWIRE_DP3_CH4_INPUT			0x0004C7C
+#define CS35L56_SWIRE_DP3_CH5_INPUT			0x0004C80
+#define CS35L56_SWIRE_DP3_CH6_INPUT			0x0004C84
+#define CS35L56_IRQ1_CFG				0x000E000
+#define CS35L56_IRQ1_STATUS				0x000E004
+#define CS35L56_IRQ1_EINT_1				0x000E010
+#define CS35L56_IRQ1_EINT_2				0x000E014
+#define CS35L56_IRQ1_EINT_4				0x000E01C
+#define CS35L56_IRQ1_EINT_8				0x000E02C
+#define CS35L56_IRQ1_EINT_18				0x000E054
+#define CS35L56_IRQ1_EINT_20				0x000E05C
+#define CS35L56_IRQ1_MASK_1				0x000E090
+#define CS35L56_IRQ1_MASK_2				0x000E094
+#define CS35L56_IRQ1_MASK_4				0x000E09C
+#define CS35L56_IRQ1_MASK_8				0x000E0AC
+#define CS35L56_IRQ1_MASK_18				0x000E0D4
+#define CS35L56_IRQ1_MASK_20				0x000E0DC
+#define CS35L56_DSP_VIRTUAL1_MBOX_1			0x0011020
+#define CS35L56_DSP_VIRTUAL1_MBOX_2			0x0011024
+#define CS35L56_DSP_VIRTUAL1_MBOX_3			0x0011028
+#define CS35L56_DSP_VIRTUAL1_MBOX_4			0x001102C
+#define CS35L56_DSP_VIRTUAL1_MBOX_5			0x0011030
+#define CS35L56_DSP_VIRTUAL1_MBOX_6			0x0011034
+#define CS35L56_DSP_VIRTUAL1_MBOX_7			0x0011038
+#define CS35L56_DSP_VIRTUAL1_MBOX_8			0x001103C
+#define CS35L56_DSP_RESTRICT_STS1			0x00190F0
+#define CS35L56_DSP1_XMEM_PACKED_0			0x2000000
+#define CS35L56_DSP1_XMEM_PACKED_6143			0x2005FFC
+#define CS35L56_DSP1_XMEM_UNPACKED32_0			0x2400000
+#define CS35L56_DSP1_XMEM_UNPACKED32_4095		0x2403FFC
+#define CS35L56_DSP1_SYS_INFO_ID			0x25E0000
+#define CS35L56_DSP1_SYS_INFO_END			0x25E004C
+#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0		0x25E2040
+#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1		0x25E2044
+#define CS35L56_DSP1_XMEM_UNPACKED24_0			0x2800000
+#define CS35L56_DSP1_HALO_STATE_A1			0x2801E58
+#define CS35L56_DSP1_HALO_STATE				0x28021E0
+#define CS35L56_DSP1_PM_CUR_STATE_A1			0x2804000
+#define CS35L56_DSP1_PM_CUR_STATE			0x2804308
+#define CS35L56_DSP1_XMEM_UNPACKED24_8191		0x2807FFC
+#define CS35L56_DSP1_CORE_BASE				0x2B80000
+#define CS35L56_DSP1_SCRATCH1				0x2B805C0
+#define CS35L56_DSP1_SCRATCH2				0x2B805C8
+#define CS35L56_DSP1_SCRATCH3				0x2B805D0
+#define CS35L56_DSP1_SCRATCH4				0x2B805D8
+#define CS35L56_DSP1_YMEM_PACKED_0			0x2C00000
+#define CS35L56_DSP1_YMEM_PACKED_4604			0x2C047F0
+#define CS35L56_DSP1_YMEM_UNPACKED32_0			0x3000000
+#define CS35L56_DSP1_YMEM_UNPACKED32_3070		0x3002FF8
+#define CS35L56_DSP1_YMEM_UNPACKED24_0			0x3400000
+#define CS35L56_MAIN_RENDER_USER_MUTE			0x3400024
+#define CS35L56_MAIN_RENDER_USER_VOLUME			0x340002C
+#define CS35L56_MAIN_POSTURE_NUMBER			0x3400094
+#define CS35L56_TRANSDUCER_ACTUAL_PS			0x3400150
+#define CS35L56_DSP1_YMEM_UNPACKED24_6141		0x3405FF4
+#define CS35L56_DSP1_PMEM_0				0x3800000
+#define CS35L56_DSP1_PMEM_5114				0x3804FE8
+
+/* DEVID */
+#define CS35L56_DEVID_MASK				0x00FFFFFF
+
+/* REVID */
+#define CS35L56_AREVID_MASK				0x000000F0
+#define CS35L56_MTLREVID_MASK				0x0000000F
+#define CS35L56_REVID_B0				0x000000B0
+
+/* ASP_ENABLES1 */
+#define CS35L56_ASP_RX2_EN_SHIFT			17
+#define CS35L56_ASP_RX1_EN_SHIFT			16
+#define CS35L56_ASP_TX4_EN_SHIFT			3
+#define CS35L56_ASP_TX3_EN_SHIFT			2
+#define CS35L56_ASP_TX2_EN_SHIFT			1
+#define CS35L56_ASP_TX1_EN_SHIFT			0
+
+/* ASP_CONTROL1 */
+#define CS35L56_ASP_BCLK_FREQ_MASK			0x0000003F
+#define CS35L56_ASP_BCLK_FREQ_SHIFT			0
+
+/* ASP_CONTROL2 */
+#define CS35L56_ASP_RX_WIDTH_MASK			0xFF000000
+#define CS35L56_ASP_RX_WIDTH_SHIFT			24
+#define CS35L56_ASP_TX_WIDTH_MASK			0x00FF0000
+#define CS35L56_ASP_TX_WIDTH_SHIFT			16
+#define CS35L56_ASP_FMT_MASK				0x00000700
+#define CS35L56_ASP_FMT_SHIFT				8
+#define CS35L56_ASP_BCLK_INV_MASK			0x00000040
+#define CS35L56_ASP_FSYNC_INV_MASK			0x00000004
+
+/* ASP_CONTROL3 */
+#define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK			0x00000003
+
+/* ASP_DATA_CONTROL1 */
+#define CS35L56_ASP_TX_WL_MASK				0x0000003F
+
+/* ASP_DATA_CONTROL5 */
+#define CS35L56_ASP_RX_WL_MASK				0x0000003F
+
+/* ASPTXn_INPUT */
+#define CS35L56_ASP_TXn_SRC_MASK			0x0000007F
+
+/* SWIRETX[1..7]_SRC SDWTXn INPUT */
+#define CS35L56_SWIRETXn_SRC_MASK			0x0000007F
+
+/* IRQ1_STATUS */
+#define CS35L56_IRQ1_STS_MASK				0x00000001
+
+/* IRQ1_EINT_1 */
+#define CS35L56_AMP_SHORT_ERR_EINT1_MASK		0x80000000
+
+/* IRQ1_EINT_2 */
+#define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK		0x00200000
+
+/* IRQ1_EINT_4 */
+#define CS35L56_OTP_BOOT_DONE_MASK			0x00000002
+
+/* IRQ1_EINT_8 */
+#define CS35L56_TEMP_ERR_EINT1_MASK			0x80000000
+
+/* Mixer input sources */
+#define CS35L56_INPUT_SRC_NONE				0x00
+#define CS35L56_INPUT_SRC_ASP1RX1			0x08
+#define CS35L56_INPUT_SRC_ASP1RX2			0x09
+#define CS35L56_INPUT_SRC_VMON				0x18
+#define CS35L56_INPUT_SRC_IMON				0x19
+#define CS35L56_INPUT_SRC_ERR_VOL			0x20
+#define CS35L56_INPUT_SRC_CLASSH			0x21
+#define CS35L56_INPUT_SRC_VDDBMON			0x28
+#define CS35L56_INPUT_SRC_VBSTMON			0x29
+#define CS35L56_INPUT_SRC_DSP1TX1			0x32
+#define CS35L56_INPUT_SRC_DSP1TX2			0x33
+#define CS35L56_INPUT_SRC_DSP1TX3			0x34
+#define CS35L56_INPUT_SRC_DSP1TX4			0x35
+#define CS35L56_INPUT_SRC_DSP1TX5			0x36
+#define CS35L56_INPUT_SRC_DSP1TX6			0x37
+#define CS35L56_INPUT_SRC_DSP1TX7			0x38
+#define CS35L56_INPUT_SRC_DSP1TX8			0x39
+#define CS35L56_INPUT_SRC_TEMPMON			0x3A
+#define CS35L56_INPUT_SRC_INTERPOLATOR			0x40
+#define CS35L56_INPUT_SRC_SWIRE_RX1			0x44
+#define CS35L56_INPUT_SRC_SWIRE_RX2			0x45
+#define CS35L56_INPUT_SRC_SWIRE_RX3			0x46
+#define CS35L56_INPUT_MASK				0x7F
+
+#define CS35L56_NUM_INPUT_SRC				22
+
+/* ASP formats */
+#define CS35L56_ASP_FMT_DSP_A				0
+#define CS35L56_ASP_FMT_I2S				2
+
+/* ASP HiZ modes */
+#define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ			3
+
+/* MAIN_RENDER_ACTUAL_PS */
+#define CS35L56_PS0					0
+#define CS35L56_PS3					3
+
+/* CS35L56_DSP_RESTRICT_STS1 */
+#define CS35L56_RESTRICTED_MASK				0x7
+
+/* CS35L56_MAIN_RENDER_USER_MUTE */
+#define CS35L56_MAIN_RENDER_USER_MUTE_MASK		1
+
+/* CS35L56_MAIN_RENDER_USER_VOLUME */
+#define CS35L56_MAIN_RENDER_USER_VOLUME_MIN		-400
+#define CS35L56_MAIN_RENDER_USER_VOLUME_MAX		400
+#define CS35L56_MAIN_RENDER_USER_VOLUME_MASK		0x0000FFC0
+#define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT		6
+#define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT		9
+
+/* CS35L56_MAIN_POSTURE_NUMBER */
+#define CS35L56_MAIN_POSTURE_MIN			0
+#define CS35L56_MAIN_POSTURE_MAX			255
+#define CS35L56_MAIN_POSTURE_MASK			CS35L56_MAIN_POSTURE_MAX
+
+/* Software Values */
+#define CS35L56_HALO_STATE_SHUTDOWN			1
+#define CS35L56_HALO_STATE_BOOT_DONE			2
+
+#define CS35L56_MBOX_CMD_AUDIO_PLAY			0x0B000001
+#define CS35L56_MBOX_CMD_AUDIO_PAUSE			0x0B000002
+#define CS35L56_MBOX_CMD_HIBERNATE_NOW			0x02000001
+#define CS35L56_MBOX_CMD_WAKEUP				0x02000002
+#define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE		0x02000003
+#define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE		0x02000004
+#define CS35L56_MBOX_CMD_SHUTDOWN			0x02000005
+#define CS35L56_MBOX_CMD_SYSTEM_RESET			0x02000007
+
+#define CS35L56_MBOX_TIMEOUT_US				5000
+#define CS35L56_MBOX_POLL_US				250
+
+#define CS35L56_PS0_POLL_US				500
+#define CS35L56_PS0_TIMEOUT_US				50000
+#define CS35L56_PS3_POLL_US				500
+#define CS35L56_PS3_TIMEOUT_US				300000
+
+#define CS35L56_CONTROL_PORT_READY_US			2200
+#define CS35L56_HALO_STATE_POLL_US			1000
+#define CS35L56_HALO_STATE_TIMEOUT_US			50000
+#define CS35L56_HIBERNATE_WAKE_POLL_US			500
+#define CS35L56_HIBERNATE_WAKE_TIMEOUT_US		5000
+#define CS35L56_RESET_PULSE_MIN_US			1100
+
+#define CS35L56_SDW1_PLAYBACK_PORT			1
+#define CS35L56_SDW1_CAPTURE_PORT			3
+
+#define CS35L56_NUM_BULK_SUPPLIES			3
+#define CS35L56_NUM_DSP_REGIONS				5
+
+extern struct regmap_config cs35l56_regmap_i2c;
+extern struct regmap_config cs35l56_regmap_spi;
+extern struct regmap_config cs35l56_regmap_sdw;
+
+extern const struct cs_dsp_region cs35l56_dsp1_regions[CS35L56_NUM_DSP_REGIONS];
+extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC];
+extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC];
+
+void cs35l56_patch(struct device *dev, struct regmap *regmap, u8 revid);
+void cs35l56_reread_firmware_registers(struct device *dev, struct regmap *regmap);
+int cs35l56_get_bclk_freq_id(unsigned int freq);
+void cs35l56_fill_supply_names(struct regulator_bulk_data *data);
+
+#endif /* ifndef __CS35L56_H */

sound/soc/codecs/Kconfig

@@ -68,6 +68,9 @@ config SND_SOC_ALL_CODECS
 	imply SND_SOC_CS35L41_I2C
 	imply SND_SOC_CS35L45_I2C
 	imply SND_SOC_CS35L45_SPI
+	imply SND_SOC_CS35L56_I2C
+	imply SND_SOC_CS35L56_SPI
+	imply SND_SOC_CS35L56_SDW
 	imply SND_SOC_CS42L42
 	imply SND_SOC_CS42L42_SDW
 	imply SND_SOC_CS42L51_I2C
@@ -364,6 +367,7 @@ config SND_SOC_WM_ADSP
 	default y if SND_SOC_WM2200=y
 	default y if SND_SOC_CS35L41_SPI=y
 	default y if SND_SOC_CS35L41_I2C=y
+	default y if SND_SOC_CS35L56=y
 	default m if SND_SOC_MADERA=m
 	default m if SND_SOC_CS47L24=m
 	default m if SND_SOC_WM5102=m
@@ -371,6 +375,7 @@ config SND_SOC_WM_ADSP
 	default m if SND_SOC_WM2200=m
 	default m if SND_SOC_CS35L41_SPI=m
 	default m if SND_SOC_CS35L41_I2C=m
+	default m if SND_SOC_CS35L56=m
 
 config SND_SOC_AB8500_CODEC
 	tristate
@@ -711,6 +716,41 @@ config SND_SOC_CS35L45_I2C
 	  Enable support for Cirrus Logic CS35L45 smart speaker amplifier
 	  with I2C control.
 
+config SND_SOC_CS35L56
+	tristate
+
+config SND_SOC_CS35L56_SHARED
+	tristate
+
+config SND_SOC_CS35L56_I2C
+	tristate "Cirrus Logic CS35L56 CODEC (I2C)"
+	depends on I2C
+	depends on SOUNDWIRE || !SOUNDWIRE
+	select REGMAP_I2C
+	select SND_SOC_CS35L56
+	select SND_SOC_CS35L56_SHARED
+	help
+	  Enable support for Cirrus Logic CS35L56 boosted amplifier with I2C control
+
+config SND_SOC_CS35L56_SPI
+	tristate "Cirrus Logic CS35L56 CODEC (SPI)"
+	depends on SPI_MASTER
+	depends on SOUNDWIRE || !SOUNDWIRE
+	select REGMAP_SPI
+	select SND_SOC_CS35L56
+	select SND_SOC_CS35L56_SHARED
+	help
+	  Enable support for Cirrus Logic CS35L56 boosted amplifier with SPI control
+
+config SND_SOC_CS35L56_SDW
+	tristate "Cirrus Logic CS35L56 CODEC (SDW)"
+	depends on SOUNDWIRE
+	select REGMAP
+	select SND_SOC_CS35L56
+	select SND_SOC_CS35L56_SHARED
+	help
+	  Enable support for Cirrus Logic CS35L56 boosted amplifier with SoundWire control
+
 config SND_SOC_CS42L42_CORE
 	tristate
 

sound/soc/codecs/Makefile

@@ -66,6 +66,11 @@ snd-soc-cs35l41-i2c-objs := cs35l41-i2c.o
 snd-soc-cs35l45-objs := cs35l45.o cs35l45-tables.o
 snd-soc-cs35l45-spi-objs := cs35l45-spi.o
 snd-soc-cs35l45-i2c-objs := cs35l45-i2c.o
+snd-soc-cs35l56-objs := cs35l56.o
+snd-soc-cs35l56-shared-objs := cs35l56-shared.o
+snd-soc-cs35l56-i2c-objs := cs35l56-i2c.o
+snd-soc-cs35l56-spi-objs := cs35l56-spi.o
+snd-soc-cs35l56-sdw-objs := cs35l56-sdw.o
 snd-soc-cs42l42-objs := cs42l42.o
 snd-soc-cs42l42-i2c-objs := cs42l42-i2c.o
 snd-soc-cs42l42-sdw-objs := cs42l42-sdw.o
@@ -433,6 +438,11 @@ obj-$(CONFIG_SND_SOC_CS35L41_I2C)	+= snd-soc-cs35l41-i2c.o
 obj-$(CONFIG_SND_SOC_CS35L45)	+= snd-soc-cs35l45.o
 obj-$(CONFIG_SND_SOC_CS35L45_SPI)	+= snd-soc-cs35l45-spi.o
 obj-$(CONFIG_SND_SOC_CS35L45_I2C)	+= snd-soc-cs35l45-i2c.o
+obj-$(CONFIG_SND_SOC_CS35L56)	+= snd-soc-cs35l56.o
+obj-$(CONFIG_SND_SOC_CS35L56_SHARED)	+= snd-soc-cs35l56-shared.o
+obj-$(CONFIG_SND_SOC_CS35L56_I2C)	+= snd-soc-cs35l56-i2c.o
+obj-$(CONFIG_SND_SOC_CS35L56_SPI)	+= snd-soc-cs35l56-spi.o
+obj-$(CONFIG_SND_SOC_CS35L56_SDW)	+= snd-soc-cs35l56-sdw.o
 obj-$(CONFIG_SND_SOC_CS42L42_CORE)	+= snd-soc-cs42l42.o
 obj-$(CONFIG_SND_SOC_CS42L42)	+= snd-soc-cs42l42-i2c.o
 obj-$(CONFIG_SND_SOC_CS42L42_SDW)	+= snd-soc-cs42l42-sdw.o

sound/soc/codecs/cs35l56-i2c.c

@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// CS35L56 ALSA SoC audio driver I2C binding
+//
+// Copyright (C) 2023 Cirrus Logic, Inc. and
+//                    Cirrus Logic International Semiconductor Ltd.
+
+#include <linux/acpi.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "cs35l56.h"
+
+static int cs35l56_i2c_probe(struct i2c_client *client)
+{
+	struct cs35l56_private *cs35l56;
+	struct device *dev = &client->dev;
+	const struct regmap_config *regmap_config = &cs35l56_regmap_i2c;
+	int ret;
+
+	cs35l56 = devm_kzalloc(dev, sizeof(struct cs35l56_private), GFP_KERNEL);
+	if (!cs35l56)
+		return -ENOMEM;
+
+	cs35l56->dev = dev;
+	cs35l56->irq = client->irq;
+	cs35l56->can_hibernate = true;
+
+	i2c_set_clientdata(client, cs35l56);
+	cs35l56->regmap = devm_regmap_init_i2c(client, regmap_config);
+	if (IS_ERR(cs35l56->regmap)) {
+		ret = PTR_ERR(cs35l56->regmap);
+		return dev_err_probe(cs35l56->dev, ret, "Failed to allocate register map\n");
+	}
+
+	ret = cs35l56_common_probe(cs35l56);
+	if (ret != 0)
+		return ret;
+
+	ret = cs35l56_init(cs35l56);
+	if (ret == 0)
+		ret = cs35l56_irq_request(cs35l56);
+	if (ret < 0)
+		cs35l56_remove(cs35l56);
+
+	return ret;
+}
+
+static void cs35l56_i2c_remove(struct i2c_client *client)
+{
+	struct cs35l56_private *cs35l56 = i2c_get_clientdata(client);
+
+	cs35l56_remove(cs35l56);
+}
+
+static const struct i2c_device_id cs35l56_id_i2c[] = {
+	{ "cs35l56", 0 },
+	{}
+};
+MODULE_DEVICE_TABLE(i2c, cs35l56_id_i2c);
+
+static struct i2c_driver cs35l56_i2c_driver = {
+	.driver = {
+		.name		= "cs35l56",
+		.pm = &cs35l56_pm_ops_i2c_spi,
+	},
+	.id_table	= cs35l56_id_i2c,
+	.probe_new	= cs35l56_i2c_probe,
+	.remove		= cs35l56_i2c_remove,
+};
+
+module_i2c_driver(cs35l56_i2c_driver);
+
+MODULE_DESCRIPTION("ASoC CS35L56 I2C driver");
+MODULE_IMPORT_NS(SND_SOC_CS35L56_CORE);
+MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED);
+MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
+MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
+MODULE_LICENSE("GPL");

sound/soc/codecs/cs35l56-sdw.c

@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// CS35L56 ALSA SoC audio driver SoundWire binding
+//
+// Copyright (C) 2023 Cirrus Logic, Inc. and
+//                    Cirrus Logic International Semiconductor Ltd.
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/soundwire/sdw.h>
+#include <linux/soundwire/sdw_registers.h>
+#include <linux/soundwire/sdw_type.h>
+#include <linux/swab.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include "cs35l56.h"
+
+/* Register addresses are offset when sent over SoundWire */
+#define CS35L56_SDW_ADDR_OFFSET		0x8000
+
+static int cs35l56_sdw_read_one(struct sdw_slave *peripheral, unsigned int reg, void *buf)
+{
+	int ret;
+
+	ret = sdw_nread_no_pm(peripheral, reg, 4, (u8 *)buf);
+	if (ret != 0) {
+		dev_err(&peripheral->dev, "Read failed @%#x:%d\n", reg, ret);
+		return ret;
+	}
+
+	swab32s((u32 *)buf);
+
+	return 0;
+}
+
+static int cs35l56_sdw_read(void *context, const void *reg_buf,
+			    const size_t reg_size, void *val_buf,
+			    size_t val_size)
+{
+	struct sdw_slave *peripheral = context;
+	u8 *buf8 = val_buf;
+	unsigned int reg, bytes;
+	int ret;
+
+	reg = le32_to_cpu(*(const __le32 *)reg_buf);
+	reg += CS35L56_SDW_ADDR_OFFSET;
+
+	if (val_size == 4)
+		return cs35l56_sdw_read_one(peripheral, reg, val_buf);
+
+	while (val_size) {
+		bytes = SDW_REG_NO_PAGE - (reg & SDW_REGADDR); /* to end of page */
+		if (bytes > val_size)
+			bytes = val_size;
+
+		ret = sdw_nread_no_pm(peripheral, reg, bytes, buf8);
+		if (ret != 0) {
+			dev_err(&peripheral->dev, "Read failed @%#x..%#x:%d\n",
+				reg, reg + bytes - 1, ret);
+			return ret;
+		}
+
+		swab32_array((u32 *)buf8, bytes / 4);
+		val_size -= bytes;
+		reg += bytes;
+		buf8 += bytes;
+	}
+
+	return 0;
+}
+
+static inline void cs35l56_swab_copy(void *dest, const void *src, size_t nbytes)
+{
+	u32 *dest32 = dest;
+	const u32 *src32 = src;
+
+	for (; nbytes > 0; nbytes -= 4)
+		*dest32++ = swab32(*src32++);
+}
+
+static int cs35l56_sdw_write_one(struct sdw_slave *peripheral, unsigned int reg, const void *buf)
+{
+	u32 val_le = swab32(*(u32 *)buf);
+	int ret;
+
+	ret = sdw_nwrite_no_pm(peripheral, reg, 4, (u8 *)&val_le);
+	if (ret != 0) {
+		dev_err(&peripheral->dev, "Write failed @%#x:%d\n", reg, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int cs35l56_sdw_gather_write(void *context,
+				    const void *reg_buf, size_t reg_size,
+				    const void *val_buf, size_t val_size)
+{
+	struct sdw_slave *peripheral = context;
+	const u8 *src_be = val_buf;
+	u32 val_le_buf[64];	/* Define u32 so it is 32-bit aligned */
+	unsigned int reg, bytes;
+	int ret;
+
+	reg = le32_to_cpu(*(const __le32 *)reg_buf);
+	reg += CS35L56_SDW_ADDR_OFFSET;
+
+	if (val_size == 4)
+		return cs35l56_sdw_write_one(peripheral, reg, src_be);
+
+	while (val_size) {
+		bytes = SDW_REG_NO_PAGE - (reg & SDW_REGADDR); /* to end of page */
+		if (bytes > val_size)
+			bytes = val_size;
+		if (bytes > sizeof(val_le_buf))
+			bytes = sizeof(val_le_buf);
+
+		cs35l56_swab_copy(val_le_buf, src_be, bytes);
+
+		ret = sdw_nwrite_no_pm(peripheral, reg, bytes, (u8 *)val_le_buf);
+		if (ret != 0) {
+			dev_err(&peripheral->dev, "Write failed @%#x..%#x:%d\n",
+				reg, reg + bytes - 1, ret);
+			return ret;
+		}
+
+		val_size -= bytes;
+		reg += bytes;
+		src_be += bytes;
+	}
+
+	return 0;
+}
+
+static int cs35l56_sdw_write(void *context, const void *val_buf, size_t val_size)
+{
+	const u8 *src_buf = val_buf;
+
+	/* First word of val_buf contains the destination address */
+	return cs35l56_sdw_gather_write(context, &src_buf[0], 4, &src_buf[4], val_size - 4);
+}
+
+/*
+ * Registers are big-endian on I2C and SPI but little-endian on SoundWire.
+ * Exported firmware controls are big-endian on I2C/SPI but little-endian on
+ * SoundWire. Firmware files are always big-endian and are opaque blobs.
+ * Present a big-endian regmap and hide the endianness swap, so that the ALSA
+ * byte controls always have the same byte order, and firmware file blobs
+ * can be written verbatim.
+ */
+static const struct regmap_bus cs35l56_regmap_bus_sdw = {
+	.read = cs35l56_sdw_read,
+	.write = cs35l56_sdw_write,
+	.gather_write = cs35l56_sdw_gather_write,
+	.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
+	.val_format_endian_default = REGMAP_ENDIAN_BIG,
+};
+
+static void cs35l56_sdw_init(struct sdw_slave *peripheral)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
+	int ret;
+
+	pm_runtime_get_noresume(cs35l56->dev);
+
+	regcache_cache_only(cs35l56->regmap, false);
+
+	ret = cs35l56_init(cs35l56);
+	if (ret < 0) {
+		regcache_cache_only(cs35l56->regmap, true);
+		goto out;
+	}
+
+	/*
+	 * cs35l56_init can return with !init_done if it triggered
+	 * a soft reset.
+	 */
+	if (cs35l56->init_done) {
+		/* Enable SoundWire interrupts */
+		sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_MASK_1,
+				CS35L56_SDW_INT_MASK_CODEC_IRQ);
+	}
+
+out:
+	pm_runtime_mark_last_busy(cs35l56->dev);
+	pm_runtime_put_autosuspend(cs35l56->dev);
+}
+
+static int cs35l56_sdw_interrupt(struct sdw_slave *peripheral,
+				 struct sdw_slave_intr_status *status)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
+
+	/* SoundWire core holds our pm_runtime when calling this function. */
+
+	dev_dbg(cs35l56->dev, "int control_port=%#x\n", status->control_port);
+
+	if ((status->control_port & SDW_SCP_INT1_IMPL_DEF) == 0)
+		return 0;
+
+	/*
+	 * Prevent bus manager suspending and possibly issuing a
+	 * bus-reset before the queued work has run.
+	 */
+	pm_runtime_get_noresume(cs35l56->dev);
+
+	/*
+	 * Mask and clear until it has been handled. The read of GEN_INT_STAT_1
+	 * is required as per the SoundWire spec for interrupt status bits
+	 * to clear. GEN_INT_MASK_1 masks the _inputs_ to GEN_INT_STAT1.
+	 * None of the interrupts are time-critical so use the
+	 * power-efficient queue.
+	 */
+	sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0);
+	sdw_read_no_pm(peripheral, CS35L56_SDW_GEN_INT_STAT_1);
+	sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF);
+	queue_work(system_power_efficient_wq, &cs35l56->sdw_irq_work);
+
+	return 0;
+}
+
+static void cs35l56_sdw_irq_work(struct work_struct *work)
+{
+	struct cs35l56_private *cs35l56 = container_of(work,
+						       struct cs35l56_private,
+						       sdw_irq_work);
+
+	cs35l56_irq(-1, cs35l56);
+
+	/* unmask interrupts */
+	if (!cs35l56->sdw_irq_no_unmask)
+		sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1,
+				CS35L56_SDW_INT_MASK_CODEC_IRQ);
+
+	pm_runtime_put_autosuspend(cs35l56->dev);
+}
+
+static int cs35l56_sdw_read_prop(struct sdw_slave *peripheral)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
+	struct sdw_slave_prop *prop = &peripheral->prop;
+	struct sdw_dpn_prop *ports;
+
+	ports = devm_kcalloc(cs35l56->dev, 2, sizeof(*ports), GFP_KERNEL);
+	if (!ports)
+		return -ENOMEM;
+
+	prop->source_ports = BIT(CS35L56_SDW1_CAPTURE_PORT);
+	prop->sink_ports = BIT(CS35L56_SDW1_PLAYBACK_PORT);
+	prop->paging_support = true;
+	prop->clk_stop_mode1 = false;
+	prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
+	prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY | SDW_SCP_INT1_IMPL_DEF;
+
+	/* DP1 - playback */
+	ports[0].num = CS35L56_SDW1_PLAYBACK_PORT;
+	ports[0].type = SDW_DPN_FULL;
+	ports[0].ch_prep_timeout = 10;
+	prop->sink_dpn_prop = &ports[0];
+
+	/* DP3 - capture */
+	ports[1].num = CS35L56_SDW1_CAPTURE_PORT;
+	ports[1].type = SDW_DPN_FULL;
+	ports[1].ch_prep_timeout = 10;
+	prop->src_dpn_prop = &ports[1];
+
+	return 0;
+}
+
+static int cs35l56_sdw_update_status(struct sdw_slave *peripheral,
+				     enum sdw_slave_status status)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
+
+	switch (status) {
+	case SDW_SLAVE_ATTACHED:
+		dev_dbg(cs35l56->dev, "%s: ATTACHED\n", __func__);
+		if (cs35l56->sdw_attached)
+			break;
+
+		if (!cs35l56->init_done || cs35l56->soft_resetting)
+			cs35l56_sdw_init(peripheral);
+
+		cs35l56->sdw_attached = true;
+		break;
+	case SDW_SLAVE_UNATTACHED:
+		dev_dbg(cs35l56->dev, "%s: UNATTACHED\n", __func__);
+		cs35l56->sdw_attached = false;
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int cs35l56_a1_kick_divider(struct cs35l56_private *cs35l56,
+				   struct sdw_slave *peripheral)
+{
+	unsigned int curr_scale_reg, next_scale_reg;
+	int curr_scale, next_scale, ret;
+
+	if (!cs35l56->init_done)
+		return 0;
+
+	if (peripheral->bus->params.curr_bank) {
+		curr_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B1;
+		next_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B0;
+	} else {
+		curr_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B0;
+		next_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B1;
+	}
+
+	/*
+	 * Current clock scale value must be different to new value.
+	 * Modify current to guarantee this. If next still has the dummy
+	 * value we wrote when it was current, the core code has not set
+	 * a new scale so restore its original good value
+	 */
+	curr_scale = sdw_read_no_pm(peripheral, curr_scale_reg);
+	if (curr_scale < 0) {
+		dev_err(cs35l56->dev, "Failed to read current clock scale: %d\n", curr_scale);
+		return curr_scale;
+	}
+
+	next_scale = sdw_read_no_pm(peripheral, next_scale_reg);
+	if (next_scale < 0) {
+		dev_err(cs35l56->dev, "Failed to read next clock scale: %d\n", next_scale);
+		return next_scale;
+	}
+
+	if (next_scale == CS35L56_SDW_INVALID_BUS_SCALE) {
+		next_scale = cs35l56->old_sdw_clock_scale;
+		ret = sdw_write_no_pm(peripheral, next_scale_reg, next_scale);
+		if (ret < 0) {
+			dev_err(cs35l56->dev, "Failed to modify current clock scale: %d\n", ret);
+			return ret;
+		}
+	}
+
+	cs35l56->old_sdw_clock_scale = curr_scale;
+	ret = sdw_write_no_pm(peripheral, curr_scale_reg, CS35L56_SDW_INVALID_BUS_SCALE);
+	if (ret < 0) {
+		dev_err(cs35l56->dev, "Failed to modify current clock scale: %d\n", ret);
+		return ret;
+	}
+
+	dev_dbg(cs35l56->dev, "Next bus scale: %#x\n", next_scale);
+
+	return 0;
+}
+
+static int cs35l56_sdw_bus_config(struct sdw_slave *peripheral,
+				  struct sdw_bus_params *params)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
+	int sclk;
+
+	sclk = params->curr_dr_freq / 2;
+	dev_dbg(cs35l56->dev, "%s: sclk=%u c=%u r=%u\n", __func__, sclk, params->col, params->row);
+
+	if (cs35l56->rev < 0xb0)
+		return cs35l56_a1_kick_divider(cs35l56, peripheral);
+
+	return 0;
+}
+
+static int __maybe_unused cs35l56_sdw_clk_stop(struct sdw_slave *peripheral,
+					       enum sdw_clk_stop_mode mode,
+					       enum sdw_clk_stop_type type)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
+
+	dev_dbg(cs35l56->dev, "%s: mode:%d type:%d\n", __func__, mode, type);
+
+	return 0;
+}
+
+static const struct sdw_slave_ops cs35l56_sdw_ops = {
+	.read_prop = cs35l56_sdw_read_prop,
+	.interrupt_callback = cs35l56_sdw_interrupt,
+	.update_status = cs35l56_sdw_update_status,
+	.bus_config = cs35l56_sdw_bus_config,
+#ifdef DEBUG
+	.clk_stop = cs35l56_sdw_clk_stop,
+#endif
+};
+
+static int __maybe_unused cs35l56_sdw_handle_unattach(struct cs35l56_private *cs35l56)
+{
+	struct sdw_slave *peripheral = cs35l56->sdw_peripheral;
+
+	if (peripheral->unattach_request) {
+		/* Cannot access registers until bus is re-initialized. */
+		dev_dbg(cs35l56->dev, "Wait for initialization_complete\n");
+		if (!wait_for_completion_timeout(&peripheral->initialization_complete,
+						 msecs_to_jiffies(5000))) {
+			dev_err(cs35l56->dev, "initialization_complete timed out\n");
+			return -ETIMEDOUT;
+		}
+
+		peripheral->unattach_request = 0;
+
+		/*
+		 * Don't call regcache_mark_dirty(), we can't be sure that the
+		 * Manager really did issue a Bus Reset.
+		 */
+	}
+
+	return 0;
+}
+
+static int __maybe_unused cs35l56_sdw_runtime_suspend(struct device *dev)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
+
+	if (!cs35l56->init_done)
+		return 0;
+
+	return cs35l56_runtime_suspend(dev);
+}
+
+static int __maybe_unused cs35l56_sdw_runtime_resume(struct device *dev)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
+	int ret;
+
+	dev_dbg(dev, "Runtime resume\n");
+
+	if (!cs35l56->init_done)
+		return 0;
+
+	ret = cs35l56_sdw_handle_unattach(cs35l56);
+	if (ret < 0)
+		return ret;
+
+	ret = cs35l56_runtime_resume_common(cs35l56);
+	if (ret)
+		return ret;
+
+	/* Re-enable SoundWire interrupts */
+	sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1,
+			CS35L56_SDW_INT_MASK_CODEC_IRQ);
+
+	return 0;
+}
+
+static int cs35l56_sdw_probe(struct sdw_slave *peripheral, const struct sdw_device_id *id)
+{
+	struct device *dev = &peripheral->dev;
+	struct cs35l56_private *cs35l56;
+	int ret;
+
+	cs35l56 = devm_kzalloc(dev, sizeof(*cs35l56), GFP_KERNEL);
+	if (!cs35l56)
+		return -ENOMEM;
+
+	cs35l56->dev = dev;
+	cs35l56->sdw_peripheral = peripheral;
+	INIT_WORK(&cs35l56->sdw_irq_work, cs35l56_sdw_irq_work);
+
+	dev_set_drvdata(dev, cs35l56);
+
+	cs35l56->regmap = devm_regmap_init(dev, &cs35l56_regmap_bus_sdw,
+					   peripheral, &cs35l56_regmap_sdw);
+	if (IS_ERR(cs35l56->regmap)) {
+		ret = PTR_ERR(cs35l56->regmap);
+		return dev_err_probe(dev, ret, "Failed to allocate register map\n");
+	}
+
+	/* Start in cache-only until device is enumerated */
+	regcache_cache_only(cs35l56->regmap, true);
+
+	ret = cs35l56_common_probe(cs35l56);
+	if (ret != 0)
+		return ret;
+
+	return 0;
+}
+
+static int cs35l56_sdw_remove(struct sdw_slave *peripheral)
+{
+	struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
+
+	/* Disable SoundWire interrupts */
+	cs35l56->sdw_irq_no_unmask = true;
+	cancel_work_sync(&cs35l56->sdw_irq_work);
+	sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0);
+	sdw_read_no_pm(peripheral, CS35L56_SDW_GEN_INT_STAT_1);
+	sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF);
+
+	return cs35l56_remove(cs35l56);
+}
+
+static const struct dev_pm_ops cs35l56_sdw_pm = {
+	SET_RUNTIME_PM_OPS(cs35l56_sdw_runtime_suspend, cs35l56_sdw_runtime_resume, NULL)
+};
+
+static const struct sdw_device_id cs35l56_sdw_id[] = {
+	SDW_SLAVE_ENTRY(0x01FA, 0x3556, 0),
+	{},
+};
+MODULE_DEVICE_TABLE(sdw, cs35l56_sdw_id);
+
+static struct sdw_driver cs35l56_sdw_driver = {
+	.driver = {
+		.name = "cs35l56",
+		.pm = &cs35l56_sdw_pm,
+	},
+	.probe = cs35l56_sdw_probe,
+	.remove = cs35l56_sdw_remove,
+	.ops = &cs35l56_sdw_ops,
+	.id_table = cs35l56_sdw_id,
+};
+
+module_sdw_driver(cs35l56_sdw_driver);
+
+MODULE_DESCRIPTION("ASoC CS35L56 SoundWire driver");
+MODULE_IMPORT_NS(SND_SOC_CS35L56_CORE);
+MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED);
+MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
+MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
+MODULE_LICENSE("GPL");

sound/soc/codecs/cs35l56-shared.c

@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Components shared between ASoC and HDA CS35L56 drivers
+//
+// Copyright (C) 2023 Cirrus Logic, Inc. and
+//                    Cirrus Logic International Semiconductor Ltd.
+
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/types.h>
+
+#include "cs35l56.h"
+
+static const struct reg_default cs35l56_reg_defaults[] = {
+	{ CS35L56_ASP1_ENABLES1,		0x00000000 },
+	{ CS35L56_ASP1_CONTROL1,		0x00000028 },
+	{ CS35L56_ASP1_CONTROL2,		0x18180200 },
+	{ CS35L56_ASP1_CONTROL3,		0x00000002 },
+	{ CS35L56_ASP1_FRAME_CONTROL1,		0x03020100 },
+	{ CS35L56_ASP1_FRAME_CONTROL5,		0x00020100 },
+	{ CS35L56_ASP1_DATA_CONTROL1,		0x00000018 },
+	{ CS35L56_ASP1_DATA_CONTROL5,		0x00000018 },
+	{ CS35L56_ASP1TX1_INPUT,		0x00000018 },
+	{ CS35L56_ASP1TX2_INPUT,		0x00000019 },
+	{ CS35L56_ASP1TX3_INPUT,		0x00000020 },
+	{ CS35L56_ASP1TX4_INPUT,		0x00000028 },
+	{ CS35L56_SWIRE_DP3_CH1_INPUT,		0x00000018 },
+	{ CS35L56_SWIRE_DP3_CH2_INPUT,		0x00000019 },
+	{ CS35L56_SWIRE_DP3_CH3_INPUT,		0x00000029 },
+	{ CS35L56_SWIRE_DP3_CH4_INPUT,		0x00000028 },
+	{ CS35L56_SWIRE_DP3_CH5_INPUT,		0x00000018 },
+	{ CS35L56_SWIRE_DP3_CH6_INPUT,		0x00000018 },
+	{ CS35L56_IRQ1_CFG,			0x00000000 },
+	{ CS35L56_IRQ1_MASK_1,			0x83ffffff },
+	{ CS35L56_IRQ1_MASK_2,			0xffff7fff },
+	{ CS35L56_IRQ1_MASK_4,			0xe0ffffff },
+	{ CS35L56_IRQ1_MASK_8,			0xfc000fff },
+	{ CS35L56_IRQ1_MASK_18,			0x1f7df0ff },
+	{ CS35L56_IRQ1_MASK_20,			0x15c00000 },
+	/* CS35L56_MAIN_RENDER_USER_MUTE - soft register, no default	*/
+	/* CS35L56_MAIN_RENDER_USER_VOLUME - soft register, no default	*/
+	/* CS35L56_MAIN_POSTURE_NUMBER - soft register, no default	*/
+};
+
+/*
+ * The Ax devices have different default register values to that of B0,
+ * establish a common set of register defaults.
+ */
+static const struct reg_sequence cs35l56_reva_patch[] = {
+	{ CS35L56_SWIRE_DP3_CH5_INPUT,	0x00000018 },
+	{ CS35L56_SWIRE_DP3_CH6_INPUT,	0x00000018 },
+};
+
+void cs35l56_patch(struct device *dev, struct regmap *regmap, u8 revid)
+{
+	int ret;
+
+	if (revid >= CS35L56_REVID_B0)
+		return;
+
+	ret = regmap_register_patch(regmap, cs35l56_reva_patch,
+				    ARRAY_SIZE(cs35l56_reva_patch));
+	if (ret)
+		dev_err(dev, "Failed to apply patch: %d\n", ret);
+}
+EXPORT_SYMBOL_NS_GPL(cs35l56_patch, SND_SOC_CS35L56_SHARED);
+
+static bool cs35l56_is_dsp_memory(unsigned int reg)
+{
+	switch (reg) {
+	case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
+	case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
+	case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
+	case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
+	case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
+	case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
+	case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case CS35L56_DEVID:
+	case CS35L56_REVID:
+	case CS35L56_RELID:
+	case CS35L56_OTPID:
+	case CS35L56_SFT_RESET:
+	case CS35L56_GLOBAL_ENABLES:
+	case CS35L56_BLOCK_ENABLES:
+	case CS35L56_BLOCK_ENABLES2:
+	case CS35L56_REFCLK_INPUT:
+	case CS35L56_GLOBAL_SAMPLE_RATE:
+	case CS35L56_ASP1_ENABLES1:
+	case CS35L56_ASP1_CONTROL1:
+	case CS35L56_ASP1_CONTROL2:
+	case CS35L56_ASP1_CONTROL3:
+	case CS35L56_ASP1_FRAME_CONTROL1:
+	case CS35L56_ASP1_FRAME_CONTROL5:
+	case CS35L56_ASP1_DATA_CONTROL1:
+	case CS35L56_ASP1_DATA_CONTROL5:
+	case CS35L56_DACPCM1_INPUT:
+	case CS35L56_DACPCM2_INPUT:
+	case CS35L56_ASP1TX1_INPUT:
+	case CS35L56_ASP1TX2_INPUT:
+	case CS35L56_ASP1TX3_INPUT:
+	case CS35L56_ASP1TX4_INPUT:
+	case CS35L56_DSP1RX1_INPUT:
+	case CS35L56_DSP1RX2_INPUT:
+	case CS35L56_SWIRE_DP3_CH1_INPUT:
+	case CS35L56_SWIRE_DP3_CH2_INPUT:
+	case CS35L56_SWIRE_DP3_CH3_INPUT:
+	case CS35L56_SWIRE_DP3_CH4_INPUT:
+	case CS35L56_SWIRE_DP3_CH5_INPUT:
+	case CS35L56_SWIRE_DP3_CH6_INPUT:
+	case CS35L56_IRQ1_CFG:
+	case CS35L56_IRQ1_STATUS:
+	case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
+	case CS35L56_IRQ1_EINT_18:
+	case CS35L56_IRQ1_EINT_20:
+	case CS35L56_IRQ1_MASK_1:
+	case CS35L56_IRQ1_MASK_2:
+	case CS35L56_IRQ1_MASK_4:
+	case CS35L56_IRQ1_MASK_8:
+	case CS35L56_IRQ1_MASK_18:
+	case CS35L56_IRQ1_MASK_20:
+	case CS35L56_DSP_VIRTUAL1_MBOX_1:
+	case CS35L56_DSP_VIRTUAL1_MBOX_2:
+	case CS35L56_DSP_VIRTUAL1_MBOX_3:
+	case CS35L56_DSP_VIRTUAL1_MBOX_4:
+	case CS35L56_DSP_VIRTUAL1_MBOX_5:
+	case CS35L56_DSP_VIRTUAL1_MBOX_6:
+	case CS35L56_DSP_VIRTUAL1_MBOX_7:
+	case CS35L56_DSP_VIRTUAL1_MBOX_8:
+	case CS35L56_DSP_RESTRICT_STS1:
+	case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
+	case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
+	case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
+	case CS35L56_DSP1_SCRATCH1:
+	case CS35L56_DSP1_SCRATCH2:
+	case CS35L56_DSP1_SCRATCH3:
+	case CS35L56_DSP1_SCRATCH4:
+		return true;
+	default:
+		return cs35l56_is_dsp_memory(reg);
+	}
+}
+
+static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
+	case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
+	case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case CS35L56_DEVID:
+	case CS35L56_REVID:
+	case CS35L56_RELID:
+	case CS35L56_OTPID:
+	case CS35L56_SFT_RESET:
+	case CS35L56_GLOBAL_ENABLES:		   /* owned by firmware */
+	case CS35L56_BLOCK_ENABLES:		   /* owned by firmware */
+	case CS35L56_BLOCK_ENABLES2:		   /* owned by firmware */
+	case CS35L56_REFCLK_INPUT:		   /* owned by firmware */
+	case CS35L56_GLOBAL_SAMPLE_RATE:	   /* owned by firmware */
+	case CS35L56_DACPCM1_INPUT:		   /* owned by firmware */
+	case CS35L56_DACPCM2_INPUT:		   /* owned by firmware */
+	case CS35L56_DSP1RX1_INPUT:		   /* owned by firmware */
+	case CS35L56_DSP1RX2_INPUT:		   /* owned by firmware */
+	case CS35L56_IRQ1_STATUS:
+	case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
+	case CS35L56_IRQ1_EINT_18:
+	case CS35L56_IRQ1_EINT_20:
+	case CS35L56_DSP_VIRTUAL1_MBOX_1:
+	case CS35L56_DSP_VIRTUAL1_MBOX_2:
+	case CS35L56_DSP_VIRTUAL1_MBOX_3:
+	case CS35L56_DSP_VIRTUAL1_MBOX_4:
+	case CS35L56_DSP_VIRTUAL1_MBOX_5:
+	case CS35L56_DSP_VIRTUAL1_MBOX_6:
+	case CS35L56_DSP_VIRTUAL1_MBOX_7:
+	case CS35L56_DSP_VIRTUAL1_MBOX_8:
+	case CS35L56_DSP_RESTRICT_STS1:
+	case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
+	case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
+	case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
+	case CS35L56_DSP1_SCRATCH1:
+	case CS35L56_DSP1_SCRATCH2:
+	case CS35L56_DSP1_SCRATCH3:
+	case CS35L56_DSP1_SCRATCH4:
+		return true;
+	case CS35L56_MAIN_RENDER_USER_MUTE:
+	case CS35L56_MAIN_RENDER_USER_VOLUME:
+	case CS35L56_MAIN_POSTURE_NUMBER:
+		return false;
+	default:
+		return cs35l56_is_dsp_memory(reg);
+	}
+}
+
+static const u32 cs35l56_firmware_registers[] = {
+	CS35L56_MAIN_RENDER_USER_MUTE,
+	CS35L56_MAIN_RENDER_USER_VOLUME,
+	CS35L56_MAIN_POSTURE_NUMBER,
+};
+
+void cs35l56_reread_firmware_registers(struct device *dev, struct regmap *regmap)
+{
+	int i;
+	unsigned int val;
+
+	for (i = 0; i < ARRAY_SIZE(cs35l56_firmware_registers); i++) {
+		regmap_read(regmap, cs35l56_firmware_registers[i], &val);
+		dev_dbg(dev, "%s: %d: %#x: %#x\n", __func__,
+			i, cs35l56_firmware_registers[i], val);
+	}
+}
+EXPORT_SYMBOL_NS_GPL(cs35l56_reread_firmware_registers, SND_SOC_CS35L56_SHARED);
+
+const struct cs_dsp_region cs35l56_dsp1_regions[] = {
+	{ .type = WMFW_HALO_PM_PACKED,	.base = CS35L56_DSP1_PMEM_0 },
+	{ .type = WMFW_HALO_XM_PACKED,	.base = CS35L56_DSP1_XMEM_PACKED_0 },
+	{ .type = WMFW_HALO_YM_PACKED,	.base = CS35L56_DSP1_YMEM_PACKED_0 },
+	{ .type = WMFW_ADSP2_XM,	.base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
+	{ .type = WMFW_ADSP2_YM,	.base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
+};
+EXPORT_SYMBOL_NS_GPL(cs35l56_dsp1_regions, SND_SOC_CS35L56_SHARED);
+
+static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
+	[0x0C] = 128000,
+	[0x0F] = 256000,
+	[0x11] = 384000,
+	[0x12] = 512000,
+	[0x15] = 768000,
+	[0x17] = 1024000,
+	[0x1A] = 1500000,
+	[0x1B] = 1536000,
+	[0x1C] = 2000000,
+	[0x1D] = 2048000,
+	[0x1E] = 2400000,
+	[0x20] = 3000000,
+	[0x21] = 3072000,
+	[0x23] = 4000000,
+	[0x24] = 4096000,
+	[0x25] = 4800000,
+	[0x27] = 6000000,
+	[0x28] = 6144000,
+	[0x29] = 6250000,
+	[0x2A] = 6400000,
+	[0x2E] = 8000000,
+	[0x2F] = 8192000,
+	[0x30] = 9600000,
+	[0x32] = 12000000,
+	[0x33] = 12288000,
+	[0x37] = 13500000,
+	[0x38] = 19200000,
+	[0x39] = 22579200,
+	[0x3B] = 24576000,
+};
+
+int cs35l56_get_bclk_freq_id(unsigned int freq)
+{
+	int i;
+
+	if (freq == 0)
+		return -EINVAL;
+
+	/* The BCLK frequency must be a valid PLL REFCLK */
+	for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
+		if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
+			return i;
+	}
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
+
+static const char * const cs35l56_supplies[/* auto-sized */] = {
+	"VDD_P",
+	"VDD_IO",
+	"VDD_A",
+};
+
+void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
+{
+	int i;
+
+	BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
+	for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
+		data[i].supply = cs35l56_supplies[i];
+}
+EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
+
+const char * const cs35l56_tx_input_texts[] = {
+	"None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
+	"VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
+	"DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
+	"INTERPOLATOR", "SDW1RX1", "SDW1RX2", "SDW2RX1",
+};
+EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
+
+const unsigned int cs35l56_tx_input_values[] = {
+	CS35L56_INPUT_SRC_NONE,
+	CS35L56_INPUT_SRC_ASP1RX1,
+	CS35L56_INPUT_SRC_ASP1RX2,
+	CS35L56_INPUT_SRC_VMON,
+	CS35L56_INPUT_SRC_IMON,
+	CS35L56_INPUT_SRC_ERR_VOL,
+	CS35L56_INPUT_SRC_CLASSH,
+	CS35L56_INPUT_SRC_VDDBMON,
+	CS35L56_INPUT_SRC_VBSTMON,
+	CS35L56_INPUT_SRC_DSP1TX1,
+	CS35L56_INPUT_SRC_DSP1TX2,
+	CS35L56_INPUT_SRC_DSP1TX3,
+	CS35L56_INPUT_SRC_DSP1TX4,
+	CS35L56_INPUT_SRC_DSP1TX5,
+	CS35L56_INPUT_SRC_DSP1TX6,
+	CS35L56_INPUT_SRC_DSP1TX7,
+	CS35L56_INPUT_SRC_DSP1TX8,
+	CS35L56_INPUT_SRC_TEMPMON,
+	CS35L56_INPUT_SRC_INTERPOLATOR,
+	CS35L56_INPUT_SRC_SWIRE_RX1,
+	CS35L56_INPUT_SRC_SWIRE_RX2,
+	CS35L56_INPUT_SRC_SWIRE_RX3,
+};
+EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
+
+struct regmap_config cs35l56_regmap_i2c = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.reg_format_endian = REGMAP_ENDIAN_BIG,
+	.val_format_endian = REGMAP_ENDIAN_BIG,
+	.max_register = CS35L56_DSP1_PMEM_5114,
+	.reg_defaults = cs35l56_reg_defaults,
+	.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
+	.volatile_reg = cs35l56_volatile_reg,
+	.readable_reg = cs35l56_readable_reg,
+	.precious_reg = cs35l56_precious_reg,
+	.cache_type = REGCACHE_RBTREE,
+};
+EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
+
+struct regmap_config cs35l56_regmap_spi = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.pad_bits = 16,
+	.reg_stride = 4,
+	.reg_format_endian = REGMAP_ENDIAN_BIG,
+	.val_format_endian = REGMAP_ENDIAN_BIG,
+	.max_register = CS35L56_DSP1_PMEM_5114,
+	.reg_defaults = cs35l56_reg_defaults,
+	.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
+	.volatile_reg = cs35l56_volatile_reg,
+	.readable_reg = cs35l56_readable_reg,
+	.precious_reg = cs35l56_precious_reg,
+	.cache_type = REGCACHE_RBTREE,
+};
+EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
+
+struct regmap_config cs35l56_regmap_sdw = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
+	.val_format_endian = REGMAP_ENDIAN_BIG,
+	.max_register = CS35L56_DSP1_PMEM_5114,
+	.reg_defaults = cs35l56_reg_defaults,
+	.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
+	.volatile_reg = cs35l56_volatile_reg,
+	.readable_reg = cs35l56_readable_reg,
+	.precious_reg = cs35l56_precious_reg,
+	.cache_type = REGCACHE_RBTREE,
+};
+EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
+
+MODULE_DESCRIPTION("ASoC CS35L56 Shared");
+MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
+MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
+MODULE_LICENSE("GPL");

sound/soc/codecs/cs35l56-spi.c

@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// CS35L56 ALSA SoC audio driver SPI binding
+//
+// Copyright (C) 2023 Cirrus Logic, Inc. and
+//                    Cirrus Logic International Semiconductor Ltd.
+
+#include <linux/acpi.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/regmap.h>
+#include <linux/spi/spi.h>
+#include <linux/types.h>
+
+#include "cs35l56.h"
+
+static int cs35l56_spi_probe(struct spi_device *spi)
+{
+	const struct regmap_config *regmap_config = &cs35l56_regmap_spi;
+	struct cs35l56_private *cs35l56;
+	int ret;
+
+	cs35l56 = devm_kzalloc(&spi->dev, sizeof(struct cs35l56_private), GFP_KERNEL);
+	if (!cs35l56)
+		return -ENOMEM;
+
+	spi_set_drvdata(spi, cs35l56);
+	cs35l56->regmap = devm_regmap_init_spi(spi, regmap_config);
+	if (IS_ERR(cs35l56->regmap)) {
+		ret = PTR_ERR(cs35l56->regmap);
+		return dev_err_probe(&spi->dev, ret, "Failed to allocate register map\n");
+		return ret;
+	}
+
+	cs35l56->dev = &spi->dev;
+	cs35l56->irq = spi->irq;
+
+	ret = cs35l56_common_probe(cs35l56);
+	if (ret != 0)
+		return ret;
+
+	ret = cs35l56_init(cs35l56);
+	if (ret == 0)
+		ret = cs35l56_irq_request(cs35l56);
+	if (ret < 0)
+		cs35l56_remove(cs35l56);
+
+	return ret;
+}
+
+static void cs35l56_spi_remove(struct spi_device *spi)
+{
+	struct cs35l56_private *cs35l56 = spi_get_drvdata(spi);
+
+	cs35l56_remove(cs35l56);
+}
+
+static const struct spi_device_id cs35l56_id_spi[] = {
+	{ "cs35l56", 0 },
+	{}
+};
+MODULE_DEVICE_TABLE(spi, cs35l56_id_spi);
+
+static struct spi_driver cs35l56_spi_driver = {
+	.driver = {
+		.name		= "cs35l56",
+		.pm = &cs35l56_pm_ops_i2c_spi,
+	},
+	.id_table	= cs35l56_id_spi,
+	.probe		= cs35l56_spi_probe,
+	.remove		= cs35l56_spi_remove,
+};
+
+module_spi_driver(cs35l56_spi_driver);
+
+MODULE_DESCRIPTION("ASoC CS35L56 SPI driver");
+MODULE_IMPORT_NS(SND_SOC_CS35L56_CORE);
+MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED);
+MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
+MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
+MODULE_LICENSE("GPL");

sound/soc/codecs/cs35l56.h

@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Driver for Cirrus Logic CS35L56 smart amp
+ *
+ * Copyright (C) 2023 Cirrus Logic, Inc. and
+ *                    Cirrus Logic International Semiconductor Ltd.
+ */
+
+#ifndef CS35L56_H
+#define CS35L56_H
+
+#include <linux/completion.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/workqueue.h>
+#include <sound/cs35l56.h>
+#include "wm_adsp.h"
+
+#define CS35L56_SDW_GEN_INT_STAT_1	0xc0
+#define CS35L56_SDW_GEN_INT_MASK_1	0xc1
+#define CS35L56_SDW_INT_MASK_CODEC_IRQ	BIT(0)
+
+#define CS35L56_SDW_INVALID_BUS_SCALE	0xf
+
+#define CS35L56_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
+#define CS35L56_TX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE \
+			    | SNDRV_PCM_FMTBIT_S32_LE)
+
+#define CS35L56_RATES (SNDRV_PCM_RATE_48000)
+
+struct sdw_slave;
+
+struct cs35l56_private {
+	struct wm_adsp dsp; /* must be first member */
+	struct work_struct dsp_work;
+	struct workqueue_struct *dsp_wq;
+	struct completion dsp_ready_completion;
+	struct mutex irq_lock;
+	struct snd_soc_component *component;
+	struct device *dev;
+	struct regmap *regmap;
+	struct regulator_bulk_data supplies[CS35L56_NUM_BULK_SUPPLIES];
+	int irq;
+	struct sdw_slave *sdw_peripheral;
+	u8 rev;
+	struct work_struct sdw_irq_work;
+	bool secured;
+	bool sdw_irq_no_unmask;
+	bool soft_resetting;
+	bool init_done;
+	bool sdw_attached;
+	bool removing;
+	bool fw_patched;
+	bool can_hibernate;
+	struct completion init_completion;
+	struct gpio_desc *reset_gpio;
+
+	u32 rx_mask;
+	u32 tx_mask;
+	u8 asp_slot_width;
+	u8 asp_slot_count;
+	bool tdm_mode;
+	bool sysclk_set;
+	u8 old_sdw_clock_scale;
+};
+
+extern const struct dev_pm_ops cs35l56_pm_ops_i2c_spi;
+
+int cs35l56_runtime_suspend(struct device *dev);
+int cs35l56_runtime_resume_common(struct cs35l56_private *cs35l56);
+irqreturn_t cs35l56_irq(int irq, void *data);
+int cs35l56_irq_request(struct cs35l56_private *cs35l56);
+int cs35l56_common_probe(struct cs35l56_private *cs35l56);
+int cs35l56_init(struct cs35l56_private *cs35l56);
+int cs35l56_remove(struct cs35l56_private *cs35l56);
+
+#endif /* ifndef CS35L56_H */