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EDAC: Remove EDAC_MM_EDAC
Move all the EDAC core functionality behind CONFIG_EDAC and get rid of that indirection. Update defconfigs which had it. While at it, fix dependencies such that EDAC depends on RAS for the tracepoints. Signed-off-by: Borislav Petkov <bp@suse.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxppc-dev@lists.ozlabs.org Cc: Chris Metcalf <cmetcalf@mellanox.com> Cc: linux-edac@vger.kernel.org
This commit is contained in:
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@ -748,7 +748,6 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
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CONFIG_LEDS_TRIGGER_TRANSIENT=y
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CONFIG_LEDS_TRIGGER_CAMERA=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_HIGHBANK_MC=y
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CONFIG_EDAC_HIGHBANK_L2=y
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CONFIG_RTC_CLASS=y
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@ -635,8 +635,7 @@ CONFIG_LEDS_TRIGGER_GPIO=m
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CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
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CONFIG_LEDS_TRIGGER_TRANSIENT=m
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CONFIG_LEDS_TRIGGER_CAMERA=m
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=m
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CONFIG_EDAC=m
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DEBUG=y
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CONFIG_RTC_DRV_DS1307=m
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@ -16,9 +16,8 @@ CONFIG_DAVICOM_PHY=y
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CONFIG_DMADEVICES=y
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CONFIG_E1000E=y
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CONFIG_E1000=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_MPC85XX=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MPC85XX=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EEPROM_LEGACY=y
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CONFIG_FB_FSL_DIU=y
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@ -155,7 +155,6 @@ CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
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CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
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CONFIG_USB_STORAGE=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_MPC85XX=y
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CONFIG_RTC_CLASS=y
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# CONFIG_RTC_INTF_PROC is not set
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@ -116,7 +116,6 @@ CONFIG_LEDS_TRIGGERS=y
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CONFIG_LEDS_TRIGGER_TIMER=y
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CONFIG_LEDS_TRIGGER_HEARTBEAT=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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CONFIG_RTC_DRV_CMOS=y
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@ -179,7 +179,6 @@ CONFIG_INFINIBAND_MTHCA=m
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CONFIG_INFINIBAND_IPOIB=m
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CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_CELL=y
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CONFIG_UIO=m
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CONFIG_EXT2_FS=y
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@ -142,7 +142,6 @@ CONFIG_USB_UHCI_HCD=y
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CONFIG_USB_SL811_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_PASEMI=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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@ -262,7 +262,6 @@ CONFIG_INFINIBAND_IPOIB_CM=y
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CONFIG_INFINIBAND_SRP=m
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CONFIG_INFINIBAND_ISER=m
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_PASEMI=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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@ -173,7 +173,6 @@ CONFIG_INFINIBAND_MTHCA=m
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CONFIG_INFINIBAND_IPOIB=m
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CONFIG_INFINIBAND_ISER=m
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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CONFIG_FS_DAX=y
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@ -988,8 +988,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=m
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CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
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CONFIG_ACCESSIBILITY=y
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CONFIG_A11Y_BRAILLE_CONSOLE=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=m
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CONFIG_EDAC=m
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CONFIG_RTC_CLASS=y
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# CONFIG_RTC_HCTOSYS is not set
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CONFIG_RTC_DRV_DS1307=m
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@ -249,7 +249,6 @@ CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_TILE=y
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CONFIG_EXT2_FS=y
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@ -358,7 +358,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y
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# CONFIG_VGA_ARB is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_TILE=y
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CONFIG_EXT2_FS=y
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@ -471,7 +471,6 @@ config ACPI_EXTLOG
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tristate "Extended Error Log support"
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depends on X86_MCE && X86_LOCAL_APIC && EDAC
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select UEFI_CPER
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select RAS
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default n
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help
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Certain usages such as Predictive Failure Analysis (PFA) require
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@ -10,8 +10,8 @@ config EDAC_SUPPORT
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bool
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menuconfig EDAC
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bool "EDAC (Error Detection And Correction) reporting"
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depends on HAS_IOMEM && EDAC_SUPPORT
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tristate "EDAC (Error Detection And Correction) reporting"
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depends on HAS_IOMEM && EDAC_SUPPORT && RAS
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help
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EDAC is designed to report errors in the core system.
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These are low-level errors that are reported in the CPU or
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@ -62,20 +62,9 @@ config EDAC_DECODE_MCE
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which occur really early upon boot, before the module infrastructure
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has been initialized.
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config EDAC_MM_EDAC
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tristate "Main Memory EDAC (Error Detection And Correction) reporting"
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select RAS
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help
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Some systems are able to detect and correct errors in main
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memory. EDAC can report statistics on memory error
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detection and correction (EDAC - or commonly referred to ECC
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errors). EDAC will also try to decode where these errors
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occurred so that a particular failing memory module can be
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replaced. If unsure, select 'Y'.
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config EDAC_GHES
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bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
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depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
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depends on ACPI_APEI_GHES && (EDAC=y)
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default y
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help
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Not all machines support hardware-driven error report. Some of those
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@ -98,7 +87,7 @@ config EDAC_GHES
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64)"
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depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
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depends on AMD_NB && EDAC_DECODE_MCE
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help
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Support for error detection and correction of DRAM ECC errors on
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the AMD64 families (>= K8) of memory controllers.
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@ -124,28 +113,28 @@ config EDAC_AMD64_ERROR_INJECTION
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config EDAC_AMD76X
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tristate "AMD 76x (760, 762, 768)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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Support for error detection and correction on the AMD 76x
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series of chipsets used with the Athlon processor.
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config EDAC_E7XXX
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tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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Support for error detection and correction on the Intel
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E7205, E7500, E7501 and E7505 server chipsets.
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config EDAC_E752X
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tristate "Intel e752x (e7520, e7525, e7320) and 3100"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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Support for error detection and correction on the Intel
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E7520, E7525, E7320 server chipsets.
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config EDAC_I82443BXGX
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tristate "Intel 82443BX/GX (440BX/GX)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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depends on BROKEN
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help
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Support for error detection and correction on the Intel
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@ -153,56 +142,56 @@ config EDAC_I82443BXGX
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config EDAC_I82875P
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tristate "Intel 82875p (D82875P, E7210)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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Support for error detection and correction on the Intel
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DP82785P and E7210 server chipsets.
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config EDAC_I82975X
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tristate "Intel 82975x (D82975x)"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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Support for error detection and correction on the Intel
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DP82975x server chipsets.
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config EDAC_I3000
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tristate "Intel 3000/3010"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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Support for error detection and correction on the Intel
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3000 and 3010 server chipsets.
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config EDAC_I3200
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tristate "Intel 3200"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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Support for error detection and correction on the Intel
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3200 and 3210 server chipsets.
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config EDAC_IE31200
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tristate "Intel e312xx"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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Support for error detection and correction on the Intel
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E3-1200 based DRAM controllers.
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config EDAC_X38
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tristate "Intel X38"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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Support for error detection and correction on the Intel
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X38 server chipsets.
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config EDAC_I5400
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tristate "Intel 5400 (Seaburg) chipsets"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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Support for error detection and correction the Intel
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i5400 MCH chipset (Seaburg).
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config EDAC_I7CORE
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tristate "Intel i7 Core (Nehalem) processors"
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depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
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depends on PCI && X86 && X86_MCE_INTEL
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help
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Support for error detection and correction the Intel
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i7 Core (Nehalem) Integrated Memory Controller that exists on
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@ -211,58 +200,56 @@ config EDAC_I7CORE
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config EDAC_I82860
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tristate "Intel 82860"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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Support for error detection and correction on the Intel
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82860 chipset.
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config EDAC_R82600
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tristate "Radisys 82600 embedded chipset"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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Support for error detection and correction on the Radisys
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82600 embedded chipset.
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config EDAC_I5000
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tristate "Intel Greencreek/Blackford chipset"
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depends on EDAC_MM_EDAC && X86 && PCI
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depends on X86 && PCI
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help
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Support for error detection and correction the Intel
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Greekcreek/Blackford chipsets.
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config EDAC_I5100
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tristate "Intel San Clemente MCH"
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depends on EDAC_MM_EDAC && X86 && PCI
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depends on X86 && PCI
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help
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Support for error detection and correction the Intel
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San Clemente MCH.
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config EDAC_I7300
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tristate "Intel Clarksboro MCH"
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depends on EDAC_MM_EDAC && X86 && PCI
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depends on X86 && PCI
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help
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Support for error detection and correction the Intel
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Clarksboro MCH (Intel 7300 chipset).
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config EDAC_SBRIDGE
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tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI_MMCONFIG
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depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
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help
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Support for error detection and correction the Intel
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Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
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config EDAC_SKX
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tristate "Intel Skylake server Integrated MC"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI_MMCONFIG
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depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
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help
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Support for error detection and correction the Intel
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Skylake server Integrated Memory Controllers.
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config EDAC_PND2
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tristate "Intel Pondicherry2"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI && X86_64 && X86_MCE_INTEL
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help
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Support for error detection and correction on the Intel
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Pondicherry2 Integrated Memory Controller. This SoC IP is
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config EDAC_MPC85XX
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tristate "Freescale MPC83xx / MPC85xx"
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depends on EDAC_MM_EDAC && FSL_SOC
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depends on FSL_SOC
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help
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Support for error detection and correction on the Freescale
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MPC8349, MPC8560, MPC8540, MPC8548, T4240
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config EDAC_LAYERSCAPE
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tristate "Freescale Layerscape DDR"
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depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
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depends on ARCH_LAYERSCAPE
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help
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Support for error detection and correction on Freescale memory
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controllers on Layerscape SoCs.
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config EDAC_MV64X60
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tristate "Marvell MV64x60"
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depends on EDAC_MM_EDAC && MV64X60
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depends on MV64X60
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help
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Support for error detection and correction on the Marvell
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MV64360 and MV64460 chipsets.
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config EDAC_PASEMI
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tristate "PA Semi PWRficient"
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depends on EDAC_MM_EDAC && PCI
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depends on PPC_PASEMI
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depends on PPC_PASEMI && PCI
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help
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Support for error detection and correction on PA Semi
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PWRficient.
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config EDAC_CELL
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tristate "Cell Broadband Engine memory controller"
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depends on EDAC_MM_EDAC && PPC_CELL_COMMON
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depends on PPC_CELL_COMMON
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help
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Support for error detection and correction on the
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Cell Broadband Engine internal memory controller
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@ -308,7 +294,7 @@ config EDAC_CELL
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config EDAC_PPC4XX
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tristate "PPC4xx IBM DDR2 Memory Controller"
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depends on EDAC_MM_EDAC && 4xx
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depends on 4xx
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help
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This enables support for EDAC on the ECC memory used
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with the IBM DDR2 memory controller found in various
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@ -317,7 +303,7 @@ config EDAC_PPC4XX
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config EDAC_AMD8131
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tristate "AMD8131 HyperTransport PCI-X Tunnel"
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depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
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depends on PCI && PPC_MAPLE
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help
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Support for error detection and correction on the
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AMD8131 HyperTransport PCI-X Tunnel chip.
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@ -326,7 +312,7 @@ config EDAC_AMD8131
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config EDAC_AMD8111
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tristate "AMD8111 HyperTransport I/O Hub"
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depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
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depends on PCI && PPC_MAPLE
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help
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Support for error detection and correction on the
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AMD8111 HyperTransport I/O Hub chip.
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@ -335,7 +321,7 @@ config EDAC_AMD8111
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config EDAC_CPC925
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tristate "IBM CPC925 Memory Controller (PPC970FX)"
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depends on EDAC_MM_EDAC && PPC64
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depends on PPC64
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help
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Support for error detection and correction on the
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IBM CPC925 Bridge and Memory Controller, which is
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@ -344,7 +330,7 @@ config EDAC_CPC925
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config EDAC_TILE
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tristate "Tilera Memory Controller"
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depends on EDAC_MM_EDAC && TILE
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depends on TILE
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default y
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help
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Support for error detection and correction on the
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@ -352,49 +338,48 @@ config EDAC_TILE
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config EDAC_HIGHBANK_MC
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tristate "Highbank Memory Controller"
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depends on EDAC_MM_EDAC && ARCH_HIGHBANK
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depends on ARCH_HIGHBANK
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help
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Support for error detection and correction on the
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Calxeda Highbank memory controller.
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config EDAC_HIGHBANK_L2
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tristate "Highbank L2 Cache"
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depends on EDAC_MM_EDAC && ARCH_HIGHBANK
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depends on ARCH_HIGHBANK
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help
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Support for error detection and correction on the
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Calxeda Highbank memory controller.
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config EDAC_OCTEON_PC
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tristate "Cavium Octeon Primary Caches"
|
||||
depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
|
||||
depends on CPU_CAVIUM_OCTEON
|
||||
help
|
||||
Support for error detection and correction on the primary caches of
|
||||
the cnMIPS cores of Cavium Octeon family SOCs.
|
||||
|
||||
config EDAC_OCTEON_L2C
|
||||
tristate "Cavium Octeon Secondary Caches (L2C)"
|
||||
depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
|
||||
depends on CAVIUM_OCTEON_SOC
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Cavium Octeon family of SOCs.
|
||||
|
||||
config EDAC_OCTEON_LMC
|
||||
tristate "Cavium Octeon DRAM Memory Controller (LMC)"
|
||||
depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
|
||||
depends on CAVIUM_OCTEON_SOC
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Cavium Octeon family of SOCs.
|
||||
|
||||
config EDAC_OCTEON_PCI
|
||||
tristate "Cavium Octeon PCI Controller"
|
||||
depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
|
||||
depends on PCI && CAVIUM_OCTEON_SOC
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Cavium Octeon family of SOCs.
|
||||
|
||||
config EDAC_THUNDERX
|
||||
tristate "Cavium ThunderX EDAC"
|
||||
depends on EDAC_MM_EDAC
|
||||
depends on ARM64
|
||||
depends on PCI
|
||||
help
|
||||
|
@ -405,7 +390,7 @@ config EDAC_THUNDERX
|
|||
|
||||
config EDAC_ALTERA
|
||||
bool "Altera SOCFPGA ECC"
|
||||
depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
|
||||
depends on EDAC=y && ARCH_SOCFPGA
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Altera SOCs. This must be selected for SDRAM ECC.
|
||||
|
@ -471,14 +456,14 @@ config EDAC_ALTERA_SDMMC
|
|||
|
||||
config EDAC_SYNOPSYS
|
||||
tristate "Synopsys DDR Memory Controller"
|
||||
depends on EDAC_MM_EDAC && ARCH_ZYNQ
|
||||
depends on ARCH_ZYNQ
|
||||
help
|
||||
Support for error detection and correction on the Synopsys DDR
|
||||
memory controller.
|
||||
|
||||
config EDAC_XGENE
|
||||
tristate "APM X-Gene SoC"
|
||||
depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST)
|
||||
depends on (ARM64 || COMPILE_TEST)
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
APM X-Gene family of SOCs.
|
||||
|
|
|
@ -6,8 +6,7 @@
|
|||
# GNU General Public License.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_EDAC) := edac_stub.o
|
||||
obj-$(CONFIG_EDAC_MM_EDAC) += edac_core.o
|
||||
obj-$(CONFIG_EDAC) := edac_stub.o edac_core.o
|
||||
|
||||
edac_core-y := edac_mc.o edac_device.o edac_mc_sysfs.o
|
||||
edac_core-y += edac_module.o edac_device_sysfs.o wq.o
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
int edac_report_status = EDAC_REPORTING_ENABLED;
|
||||
EXPORT_SYMBOL_GPL(edac_report_status);
|
||||
|
||||
static int __init edac_report_setup(char *str)
|
||||
static int __init __maybe_unused edac_report_setup(char *str)
|
||||
{
|
||||
if (!str)
|
||||
return -EINVAL;
|
||||
|
|
Loading…
Reference in New Issue
Block a user