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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: Blackfin: SMP: fix cache flush loop Blackfin: time-ts: ack gptimer sooner to avoid missing short ints Blackfin: gptimers: fix thinko when disabling timers Blackfin: SMP: make all barriers handle cache issues
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commit
e38f5b7450
@ -19,11 +19,11 @@
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* Force strict CPU ordering.
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*/
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#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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#define rmb() __asm__ __volatile__ ("" : : : "memory")
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#define wmb() __asm__ __volatile__ ("" : : : "memory")
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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#define read_barrier_depends() do { } while(0)
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define smp_read_barrier_depends() read_barrier_depends()
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#ifdef CONFIG_SMP
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asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
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@ -37,16 +37,16 @@ asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
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unsigned long new, unsigned long old);
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#ifdef __ARCH_SYNC_CORE_DCACHE
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# define smp_mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
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# define smp_rmb() do { barrier(); smp_check_barrier(); } while (0)
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# define smp_wmb() do { barrier(); smp_mark_barrier(); } while (0)
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#define smp_read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
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/* Force Core data cache coherence */
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# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
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# define rmb() do { barrier(); smp_check_barrier(); } while (0)
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# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
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# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
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#else
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# define smp_mb() barrier()
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# define smp_rmb() barrier()
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# define smp_wmb() barrier()
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#define smp_read_barrier_depends() barrier()
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# define mb() barrier()
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# define rmb() barrier()
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# define wmb() barrier()
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# define read_barrier_depends() do { } while (0)
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#endif
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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@ -99,10 +99,10 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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#else /* !CONFIG_SMP */
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define read_barrier_depends() do { } while (0)
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struct __xchg_dummy {
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unsigned long a[100];
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@ -268,7 +268,7 @@ void disable_gptimers(uint16_t mask)
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_disable_gptimers(mask);
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for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
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if (mask & (1 << i))
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group_regs[BFIN_TIMER_OCTET(i)]->status |= trun_mask[i];
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group_regs[BFIN_TIMER_OCTET(i)]->status = trun_mask[i];
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SSYNC();
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}
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EXPORT_SYMBOL(disable_gptimers);
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@ -206,8 +206,14 @@ irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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smp_mb();
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evt->event_handler(evt);
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/*
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* We want to ACK before we handle so that we can handle smaller timer
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* intervals. This way if the timer expires again while we're handling
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* things, we're more likely to see that 2nd int rather than swallowing
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* it by ACKing the int at the end of this handler.
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*/
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bfin_gptmr0_ack();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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@ -109,10 +109,23 @@ static void ipi_flush_icache(void *info)
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struct blackfin_flush_data *fdata = info;
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/* Invalidate the memory holding the bounds of the flushed region. */
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invalidate_dcache_range((unsigned long)fdata,
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(unsigned long)fdata + sizeof(*fdata));
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blackfin_dcache_invalidate_range((unsigned long)fdata,
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(unsigned long)fdata + sizeof(*fdata));
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flush_icache_range(fdata->start, fdata->end);
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/* Make sure all write buffers in the data side of the core
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* are flushed before trying to invalidate the icache. This
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* needs to be after the data flush and before the icache
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* flush so that the SSYNC does the right thing in preventing
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* the instruction prefetcher from hitting things in cached
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* memory at the wrong time -- it runs much further ahead than
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* the pipeline.
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*/
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SSYNC();
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/* ipi_flaush_icache is invoked by generic flush_icache_range,
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* so call blackfin arch icache flush directly here.
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*/
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blackfin_icache_flush_range(fdata->start, fdata->end);
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}
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static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
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