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[ARM] 5466/1: Freescale STMP platform support [5/10]

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Shared (platform) headers

Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
dmitry pervushin 2009-04-22 23:55:23 +01:00 committed by Russell King
parent 07d9714365
commit e317872ac5
17 changed files with 951 additions and 0 deletions
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18
arch/arm/plat-stmp3xxx/include/mach/clkdev.h Normal file
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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

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arch/arm/plat-stmp3xxx/include/mach/cputype.h Normal file
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/*
* Freescale STMP37XX/STMP378X CPU type detection
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_CPU_H
#define __ASM_PLAT_CPU_H
#ifdef CONFIG_ARCH_STMP37XX
#define cpu_is_stmp37xx() (1)
#else
#define cpu_is_stmp37xx() (0)
#endif
#ifdef CONFIG_ARCH_STMP378X
#define cpu_is_stmp378x() (1)
#else
#define cpu_is_stmp378x() (0)
#endif
#endif /* __ASM_PLAT_CPU_H */

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arch/arm/plat-stmp3xxx/include/mach/debug-macro.S Normal file
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/*
* Debugging macro include header
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x80000000 @ physical base address
addeq \rx, \rx, #0x00070000
movne \rx, #0xf0000000 @ virtual base
addne \rx, \rx, #0x00070000
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #0] @ data register at 0
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
bne 1001b
.endm

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arch/arm/plat-stmp3xxx/include/mach/dma.h Normal file
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/*
* Freescale STMP37XX/STMP378X DMA helper interface
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_STMP3XXX_DMA_H
#define __ASM_PLAT_STMP3XXX_DMA_H
#include <linux/platform_device.h>
#include <linux/dmapool.h>
#if !defined(MAX_PIO_WORDS)
#define MAX_PIO_WORDS (15)
#endif
#define STMP3XXX_BUS_APBH 0
#define STMP3XXX_BUS_APBX 1
#define STMP3XXX_DMA_MAX_CHANNEL 16
#define STMP3xxx_DMA(channel, bus) ((bus) * 16 + (channel))
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 32
struct stmp3xxx_dma_command {
u32 next;
u32 cmd;
union {
u32 buf_ptr;
u32 alternate;
};
u32 pio_words[MAX_PIO_WORDS];
};
struct stmp3xxx_dma_descriptor {
struct stmp3xxx_dma_command *command;
dma_addr_t handle;
/* The virtual address of the buffer pointer */
void *virtual_buf_ptr;
/* The next descriptor in a the DMA chain (optional) */
struct stmp3xxx_dma_descriptor *next_descr;
};
struct stmp37xx_circ_dma_chain {
unsigned total_count;
struct stmp3xxx_dma_descriptor *chain;
unsigned free_index;
unsigned free_count;
unsigned active_index;
unsigned active_count;
unsigned cooked_index;
unsigned cooked_count;
int bus;
unsigned channel;
};
static inline struct stmp3xxx_dma_descriptor
*stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
{
return &(chain->chain[chain->free_index]);
}
static inline struct stmp3xxx_dma_descriptor
*stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
{
return &(chain->chain[chain->cooked_index]);
}
int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
int stmp3xxx_dma_release(int ch);
int stmp3xxx_dma_allocate_command(int ch,
struct stmp3xxx_dma_descriptor *descriptor);
int stmp3xxx_dma_free_command(int ch,
struct stmp3xxx_dma_descriptor *descriptor);
void stmp3xxx_dma_continue(int channel, u32 semaphore);
void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
u32 semaphore);
int stmp3xxx_dma_running(int ch);
int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
struct stmp3xxx_dma_descriptor descriptors[],
unsigned items);
void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
unsigned count);
void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
unsigned count);
unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
int stmp3xxx_dma_read_semaphore(int ch);
void stmp3xxx_dma_init(void);
void stmp3xxx_dma_set_alt_target(int ch, int target);
void stmp3xxx_dma_suspend(void);
void stmp3xxx_dma_resume(void);
/*
* STMP37xx and STMP378x have different DMA control
* registers layout
*/
void stmp3xxx_arch_dma_freeze(int ch);
void stmp3xxx_arch_dma_unfreeze(int ch);
void stmp3xxx_arch_dma_reset_channel(int ch);
void stmp3xxx_arch_dma_enable_interrupt(int ch);
void stmp3xxx_arch_dma_clear_interrupt(int ch);
int stmp3xxx_arch_dma_is_interrupt(int ch);
static inline void stmp3xxx_dma_reset_channel(int ch)
{
stmp3xxx_arch_dma_reset_channel(ch);
}
static inline void stmp3xxx_dma_freeze(int ch)
{
stmp3xxx_arch_dma_freeze(ch);
}
static inline void stmp3xxx_dma_unfreeze(int ch)
{
stmp3xxx_arch_dma_unfreeze(ch);
}
static inline void stmp3xxx_dma_enable_interrupt(int ch)
{
stmp3xxx_arch_dma_enable_interrupt(ch);
}
static inline void stmp3xxx_dma_clear_interrupt(int ch)
{
stmp3xxx_arch_dma_clear_interrupt(ch);
}
static inline int stmp3xxx_dma_is_interrupt(int ch)
{
return stmp3xxx_arch_dma_is_interrupt(ch);
}
#endif /* __ASM_PLAT_STMP3XXX_DMA_H */

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arch/arm/plat-stmp3xxx/include/mach/gpio.h Normal file
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/*
* Freescale STMP37XX/STMP378X GPIO interface
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_GPIO_H
#define __ASM_PLAT_GPIO_H
#define ARCH_NR_GPIOS (32 * 3)
#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
#define gpio_get_value(gpio) __gpio_get_value(gpio)
#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
#include <asm-generic/gpio.h>
#endif /* __ASM_PLAT_GPIO_H */

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arch/arm/plat-stmp3xxx/include/mach/hardware.h Normal file
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/*
* This file contains the hardware definitions of the Freescale STMP3XXX
*
* Copyright (C) 2005 Sigmatel Inc
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* Where in virtual memory the IO devices (timers, system controllers
* and so on)
*/
#define IO_BASE 0xF0000000 /* VA of IO */
#define IO_SIZE 0x00100000 /* How much? */
#define IO_START 0x80000000 /* PA of IO */
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
#endif

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arch/arm/plat-stmp3xxx/include/mach/io.h Normal file
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/*
* Copyright (C) 2005 Sigmatel Inc
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif

22
arch/arm/plat-stmp3xxx/include/mach/memory.h Normal file
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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x40000000)
#endif

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arch/arm/plat-stmp3xxx/include/mach/pinmux.h Normal file
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/*
* Freescale STMP37XX/STMP378X Pin Multiplexing
*
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __PINMUX_H
#define __PINMUX_H
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/gpio.h>
#include <asm-generic/gpio.h>
/* Pin definitions */
#include "pins.h"
#include <mach/pins.h>
/*
* Each pin may be routed up to four different HW interfaces
* including GPIO
*/
enum pin_fun {
PIN_FUN1 = 0,
PIN_FUN2,
PIN_FUN3,
PIN_GPIO,
};
/*
* Each pin may have different output drive strength in range from
* 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
*/
enum pin_strength {
PIN_4MA = 0,
PIN_8MA,
PIN_12MA,
PIN_16MA,
PIN_20MA,
};
/*
* Each pin can be programmed for 1.8V or 3.3V
*/
enum pin_voltage {
PIN_1_8V = 0,
PIN_3_3V,
};
/*
* Structure to define a group of pins and their parameters
*/
struct pin_desc {
unsigned id;
enum pin_fun fun;
enum pin_strength strength;
enum pin_voltage voltage;
unsigned pullup:1;
};
struct pin_group {
struct pin_desc *pins;
int nr_pins;
};
/* Set pin drive strength */
void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
const char *label);
/* Set pin voltage */
void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
const char *label);
/* Enable pull-up resistor for a pin */
void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
/*
* Request a pin ownership, only one module (identified by @label)
* may own a pin.
*/
int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
/* Release pin */
void stmp3xxx_release_pin(unsigned id, const char *label);
void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
/*
* Each bank is associated with a number of registers to control
* pin function, drive strength, voltage and pull-up reigster. The
* number of registers of a given type depends on the number of bits
* describin particular pin.
*/
#define HW_MUXSEL_NUM 2 /* registers per bank */
#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
#define HW_DRIVE_NUM 4 /* registers per bank */
#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
#define HW_DRIVE_PIN_NUM 8 /* pins per register */
#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
struct stmp3xxx_pinmux_bank {
struct gpio_chip chip;
/* Pins allocation map */
unsigned long pin_map;
/* Pin owner names */
const char *pin_labels[32];
/* Bank registers */
void __iomem *hw_muxsel[HW_MUXSEL_NUM];
void __iomem *hw_drive[HW_DRIVE_NUM];
void __iomem *hw_pull;
void __iomem *pin2irq,
*irqlevel,
*irqpolarity,
*irqen,
*irqstat;
/* HW MUXSEL register function bit values */
u8 functions[HW_MUXSEL_PINFUN_NUM];
/*
* HW DRIVE register strength bit values:
* 0xff - requested strength is not supported for this bank
*/
u8 strengths[HW_DRIVE_PINDRV_NUM];
/* GPIO things */
void __iomem *hw_gpio_read,
*hw_gpio_set,
*hw_gpio_clr,
*hw_gpio_doe;
int irq, virq;
};
int __init stmp3xxx_pinmux_init(int virtual_irq_start);
#endif /* __PINMUX_H */

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arch/arm/plat-stmp3xxx/include/mach/pins.h Normal file
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/*
* Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
*
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_PINS_H
#define __ASM_PLAT_PINS_H
#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
/*
* Special invalid pin identificator to show a pin doesn't exist
*/
#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
#endif /* __ASM_PLAT_PINS_H */

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arch/arm/plat-stmp3xxx/include/mach/platform.h Normal file
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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_PLATFORM_H
#define __ASM_PLAT_PLATFORM_H
#include <asm/sizes.h>
/* Virtual address where registers are mapped */
#define STMP3XXX_REGS_PHBASE 0x80000000
#ifdef __ASSEMBLER__
#define STMP3XXX_REGS_BASE 0xF0000000
#else
#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
#endif
#define STMP3XXX_REGS_SIZE SZ_1M
/* Virtual address where OCRAM is mapped */
#define STMP3XXX_OCRAM_PHBASE 0x00000000
#ifdef __ASSEMBLER__
#define STMP3XXX_OCRAM_BASE 0xf1000000
#else
#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
#endif
#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
#ifdef CONFIG_ARCH_STMP37XX
#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
#endif
#ifdef CONFIG_ARCH_STMP378X
#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
#endif
#endif /* __ASM_ARCH_PLATFORM_H */

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arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h Normal file
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/*
* Freescale STMP37XX/STMP378X core structure and function declarations
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_STMP3XXX_H
#define __ASM_PLAT_STMP3XXX_H
#include <linux/irq.h>
extern struct sys_timer stmp3xxx_timer;
void stmp3xxx_init_irq(struct irq_chip *chip);
void stmp3xxx_init(void);
int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
extern struct platform_device stmp3xxx_dbguart;
struct pin_group;
void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
#endif /* __ASM_PLAT_STMP3XXX_H */

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arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h Normal file
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/*
* Freescale STMP37XX/STMP378X SoC register access interfaces
*
* The SoC registers may be accessed via:
*
* - single 32 bit address, or
* - four 32 bit addresses - general purpose, set, clear and toggle bits
*
* Multiple IP blocks (e.g. SSP, UART) provide identical register sets per
* each module
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_STMP3XXX_REGS_H
#define __ASM_PLAT_STMP3XXX_REGS_H
#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif
#include "platform.h"
#define REGS_BASE STMP3XXX_REGS_BASE
#define HW_STMP3xxx_SET 0x04
#define HW_STMP3xxx_CLR 0x08
#define HW_STMP3xxx_TOG 0x0c
#ifndef __ASSEMBLER__
#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) \
static const u32 id##_OFFSET = offset; \
static inline u32 id##_RD_NB(const void __iomem *regbase) { \
if (!rd) \
printk(KERN_ERR"%s: cannot READ at %p+%x\n", \
#id, regbase, offset); \
return __raw_readl(regbase + offset); \
} \
static inline void id##_WR_NB(void __iomem *regbase, u32 v) { \
if (!wr) \
printk(KERN_ERR"%s: cannot WRITE at %p+%x\n", \
#id, regbase, offset); \
__raw_writel(v, regbase + offset); \
} \
static inline void id##_SET_NB(void __iomem *regbase, u32 v) { \
if (!wr) \
printk(KERN_ERR"%s: cannot SET at %p+%x\n", \
#id, regbase, offset); \
if (regset) \
__raw_writel(v, regbase + \
offset + HW_STMP3xxx_SET); \
else \
__raw_writel(v | __raw_readl(regbase + offset), \
regbase + offset); \
} \
static inline void id##_CLR_NB(void __iomem *regbase, u32 v) { \
if (!wr) \
printk(KERN_ERR"%s: cannot CLR at %p+%x\n", \
#id, regbase, offset); \
if (regset) \
__raw_writel(v, regbase + \
offset + HW_STMP3xxx_CLR); \
else \
__raw_writel( \
~v & __raw_readl(regbase + offset), \
regbase + offset); \
} \
static inline void id##_TOG_NB(void __iomem *regbase, u32 v) { \
if (!wr) \
printk(KERN_ERR"%s: cannot TOG at %p+%x\n", \
#id, regbase, offset); \
if (regset) \
__raw_writel(v, regbase + \
offset + HW_STMP3xxx_TOG); \
else \
__raw_writel(v ^ __raw_readl(regbase + offset), \
regbase + offset); \
} \
static inline u32 id##_RD(void) { return id##_RD_NB(base); } \
static inline void id##_WR(u32 v) { id##_WR_NB(base, v); } \
static inline void id##_SET(u32 v) { id##_SET_NB(base, v); } \
static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); } \
static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); }
#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\
static inline u32 id##_OFFSET(int i) { \
return offset + i * step; \
} \
static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\
if (!rd) \
printk(KERN_ERR"%s(%d): can't READ at %p+%x\n", \
#id, i, regbase, offset + i * step); \
return __raw_readl(regbase + offset + i * step); \
} \
static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\
if (!wr) \
printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\
#id, i, regbase, offset + i * step); \
__raw_writel(v, regbase + offset + i * step); \
} \
static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\
if (!wr) \
printk(KERN_ERR"%s(%d): can't SET at %p+%x\n", \
#id, i, regbase, offset + i * step); \
if (regset) \
__raw_writel(v, regbase + offset + \
i * step + HW_STMP3xxx_SET); \
else \
__raw_writel(v | __raw_readl(regbase + \
offset + i * step), \
regbase + offset + i * step); \
} \
static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\
if (!wr) \
printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n", \
#id, i, regbase, offset + i * step); \
if (regset) \
__raw_writel(v, regbase + offset + \
i * step + HW_STMP3xxx_CLR); \
else \
__raw_writel(~v & __raw_readl(regbase + \
offset + i * step), \
regbase + offset + i * step); \
} \
static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\
if (!wr) \
printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n", \
#id, i, regbase, offset + i * step); \
if (regset) \
__raw_writel(v, regbase + offset + \
i * step + HW_STMP3xxx_TOG); \
else \
__raw_writel(v ^ __raw_readl(regbase + offset \
+ i * step), \
regbase + offset + i * step); \
} \
static inline u32 id##_RD(int i) \
{ \
return id##_RD_NB(base, i); \
} \
static inline void id##_WR(int i, u32 v) \
{ \
id##_WR_NB(base, i, v); \
} \
static inline void id##_SET(int i, u32 v) \
{ \
id##_SET_NB(base, i, v); \
} \
static inline void id##_CLR(int i, u32 v) \
{ \
id##_CLR_NB(base, i, v); \
} \
static inline void id##_TOG(int i, u32 v) \
{ \
id##_TOG_NB(base, i, v); \
}
#define HW_REGISTER_WO(id, base, offset)\
HW_REGISTER_FUNCS(id, base, offset, 1, 0, 1)
#define HW_REGISTER_RO(id, base, offset)\
HW_REGISTER_FUNCS(id, base, offset, 1, 1, 0)
#define HW_REGISTER(id, base, offset) \
HW_REGISTER_FUNCS(id, base, offset, 1, 1, 1)
#define HW_REGISTER_0(id, base, offset) \
HW_REGISTER_FUNCS(id, base, offset, 0, 1, 1)
#define HW_REGISTER_INDEXED(id, base, offset, step) \
HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 1, step)
#define HW_REGISTER_RO_INDEXED(id, base, offset, step) \
HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 0, step)
#define HW_REGISTER_0_INDEXED(id, base, offset, step) \
HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0, 1, 1, step)
#else /* __ASSEMBLER__ */
#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr)
#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)
#define HW_REGISTER_WO(id, base, offset)
#define HW_REGISTER_RO(id, base, offset)
#define HW_REGISTER(id, base, offset)
#define HW_REGISTER_0(id, base, offset)
#define HW_REGISTER_INDEXED(id, base, offset, step)
#define HW_REGISTER_RO_INDEXED(id, base, offset, step)
#define HW_REGISTER_0_INDEXED(id, base, offset, step)
#endif /* __ASSEMBLER__ */
#endif /* __ASM_PLAT_STMP3XXX_REGS_H */

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arch/arm/plat-stmp3xxx/include/mach/system.h Normal file
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/*
* Copyright (C) 2005 Sigmatel Inc
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/proc-fns.h>
#include <mach/regs-clkctrl.h>
#include <mach/regs-power.h>
static inline void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks
*/
cpu_do_idle();
}
static inline void arch_reset(char mode, const char *cmd)
{
/* Set BATTCHRG to default value */
HW_POWER_CHARGE_WR(0x00010000);
/* Set MINPWR to default value */
HW_POWER_MINPWR_WR(0);
/* Reset digital side of chip (but not power or RTC) */
HW_CLKCTRL_RESET_WR(BM_CLKCTRL_RESET_DIG);
/* Should not return */
}
#endif

20
arch/arm/plat-stmp3xxx/include/mach/timex.h Normal file
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/*
* Copyright (C) 1999 ARM Limited
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*
* System time clock is sourced from the 32k clock
*/
#define CLOCK_TICK_RATE (32768)

53
arch/arm/plat-stmp3xxx/include/mach/uncompress.h Normal file
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/*
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_UNCOMPRESS_H
#define __ASM_PLAT_UNCOMPRESS_H
/*
* Register includes are for when the MMU enabled; we need to define our
* own stuff here for pre-MMU use
*/
#define UARTDBG_BASE 0x80070000
#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c])
/*
* This does not append a newline
*/
static void putc(char c)
{
/* Wait for TX fifo empty */
while ((UART(6) & (1<<7)) == 0)
continue;
/* Write byte */
UART(0) = c;
/* Wait for last bit to exit the UART */
while (UART(6) & (1<<3))
continue;
}
static void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif /* __ASM_PLAT_UNCOMPRESS_H */

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arch/arm/plat-stmp3xxx/include/mach/vmalloc.h Normal file
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/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#define VMALLOC_END (0xF0000000)