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gpio: 104-idi-48: Migrate to the regmap-irq API
The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver.
For the 104-idi-48, we get an IRQ register with some status information
and basic masking, but it's broken down by banks rather than individual
GPIO. There are six banks (8 GPIO lines each) that correspond to the
lower six bits of the IRQ register (bits 0-5):
Base Address + 7 (Read): IRQ Status Register/IRQ Clear
Bit 0-5: Respective Bank IRQ Statuses
Bit 6: IRQ Status (Active Low)
Bit 7: IRQ Enable Status
Base Address + 7 (Write): IRQ Enable/Disable
Bit 0-5: Respective Bank IRQ Enable/Disable
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
William Breathitt Gray
Bartosz Golaszewski
parent
2f7e845f51
commit
e28432a773
@ -872,6 +872,8 @@ config GPIO_104_IDI_48
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tristate "ACCES 104-IDI-48 GPIO support"
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depends on PC104
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select ISA_BUS_API
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select REGMAP_MMIO
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select REGMAP_IRQ
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select GPIOLIB_IRQCHIP
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select GPIO_I8255
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help
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@ -8,17 +8,16 @@
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*/
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include "gpio-i8255.h"
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@ -38,6 +37,9 @@ static unsigned int num_irq;
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module_param_hw_array(irq, uint, irq, &num_irq, 0);
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MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
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#define IDI48_IRQ_STATUS 0x7
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#define IDI48_IRQ_ENABLE IDI48_IRQ_STATUS
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/**
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* struct idi_48_reg - device register structure
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* @port0: Port 0 Inputs
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@ -56,17 +58,11 @@ struct idi_48_reg {
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/**
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* struct idi_48_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @lock: synchronization lock to prevent I/O race conditions
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* @irq_mask: input bits affected by interrupts
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* @reg: I/O address offset for the device registers
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* @cos_enb: Change-Of-State IRQ enable boundaries mask
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*/
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struct idi_48_gpio {
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struct gpio_chip chip;
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spinlock_t lock;
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unsigned char irq_mask[6];
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struct idi_48_reg __iomem *reg;
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unsigned char cos_enb;
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};
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static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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@ -98,125 +94,65 @@ static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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return 0;
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}
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static void idi_48_irq_ack(struct irq_data *data)
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{
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}
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static void idi_48_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
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const unsigned int offset = irqd_to_hwirq(data);
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const unsigned long boundary = offset / 8;
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const unsigned long mask = BIT(offset % 8);
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unsigned long flags;
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spin_lock_irqsave(&idi48gpio->lock, flags);
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idi48gpio->irq_mask[boundary] &= ~mask;
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gpiochip_disable_irq(chip, offset);
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/* Exit early if there are still input lines with IRQ unmasked */
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if (idi48gpio->irq_mask[boundary])
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goto exit;
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idi48gpio->cos_enb &= ~BIT(boundary);
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iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
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exit:
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spin_unlock_irqrestore(&idi48gpio->lock, flags);
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}
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static void idi_48_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
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const unsigned int offset = irqd_to_hwirq(data);
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const unsigned long boundary = offset / 8;
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const unsigned long mask = BIT(offset % 8);
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unsigned int prev_irq_mask;
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unsigned long flags;
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spin_lock_irqsave(&idi48gpio->lock, flags);
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prev_irq_mask = idi48gpio->irq_mask[boundary];
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gpiochip_enable_irq(chip, offset);
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idi48gpio->irq_mask[boundary] |= mask;
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/* Exit early if IRQ was already unmasked for this boundary */
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if (prev_irq_mask)
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goto exit;
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idi48gpio->cos_enb |= BIT(boundary);
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iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
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exit:
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spin_unlock_irqrestore(&idi48gpio->lock, flags);
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}
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static int idi_48_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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/* The only valid irq types are none and both-edges */
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if (flow_type != IRQ_TYPE_NONE &&
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(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
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return -EINVAL;
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return 0;
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}
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static const struct irq_chip idi_48_irqchip = {
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.name = "104-idi-48",
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.irq_ack = idi_48_irq_ack,
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.irq_mask = idi_48_irq_mask,
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.irq_unmask = idi_48_irq_unmask,
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.irq_set_type = idi_48_irq_set_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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static const struct regmap_range idi_48_wr_ranges[] = {
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regmap_reg_range(0x0, 0x6),
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};
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static const struct regmap_range idi_48_rd_ranges[] = {
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regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x7),
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};
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static const struct regmap_range idi_48_precious_ranges[] = {
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regmap_reg_range(0x7, 0x7),
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};
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static const struct regmap_access_table idi_48_wr_table = {
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.no_ranges = idi_48_wr_ranges,
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.n_no_ranges = ARRAY_SIZE(idi_48_wr_ranges),
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};
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static const struct regmap_access_table idi_48_rd_table = {
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.yes_ranges = idi_48_rd_ranges,
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.n_yes_ranges = ARRAY_SIZE(idi_48_rd_ranges),
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};
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static const struct regmap_access_table idi_48_precious_table = {
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.yes_ranges = idi_48_precious_ranges,
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.n_yes_ranges = ARRAY_SIZE(idi_48_precious_ranges),
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};
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static const struct regmap_config idi48_regmap_config = {
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.reg_bits = 8,
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.reg_stride = 1,
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.val_bits = 8,
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.io_port = true,
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.max_register = 0x6,
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.wr_table = &idi_48_wr_table,
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.rd_table = &idi_48_rd_table,
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.precious_table = &idi_48_precious_table,
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};
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static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
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{
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struct idi_48_gpio *const idi48gpio = dev_id;
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unsigned long cos_status;
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unsigned long boundary;
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unsigned long irq_mask;
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unsigned long bit_num;
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unsigned long gpio;
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struct gpio_chip *const chip = &idi48gpio->chip;
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spin_lock(&idi48gpio->lock);
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cos_status = ioread8(&idi48gpio->reg->irq);
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/* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
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if (cos_status & BIT(6)) {
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spin_unlock(&idi48gpio->lock);
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return IRQ_NONE;
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}
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/* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
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cos_status &= 0x3F;
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for_each_set_bit(boundary, &cos_status, 6) {
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irq_mask = idi48gpio->irq_mask[boundary];
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for_each_set_bit(bit_num, &irq_mask, 8) {
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gpio = bit_num + boundary * 8;
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generic_handle_domain_irq(chip->irq.domain,
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gpio);
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}
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}
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spin_unlock(&idi48gpio->lock);
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return IRQ_HANDLED;
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}
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#define IDI48_NGPIO 48
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#define IDI48_REGMAP_IRQ(_id) \
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[_id] = { \
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.mask = BIT((_id) / 8), \
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.type = { .types_supported = IRQ_TYPE_EDGE_BOTH }, \
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}
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static const struct regmap_irq idi48_regmap_irqs[IDI48_NGPIO] = {
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IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
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IDI48_REGMAP_IRQ(3), IDI48_REGMAP_IRQ(4), IDI48_REGMAP_IRQ(5), /* 3-5 */
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IDI48_REGMAP_IRQ(6), IDI48_REGMAP_IRQ(7), IDI48_REGMAP_IRQ(8), /* 6-8 */
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IDI48_REGMAP_IRQ(9), IDI48_REGMAP_IRQ(10), IDI48_REGMAP_IRQ(11), /* 9-11 */
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IDI48_REGMAP_IRQ(12), IDI48_REGMAP_IRQ(13), IDI48_REGMAP_IRQ(14), /* 12-14 */
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IDI48_REGMAP_IRQ(15), IDI48_REGMAP_IRQ(16), IDI48_REGMAP_IRQ(17), /* 15-17 */
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IDI48_REGMAP_IRQ(18), IDI48_REGMAP_IRQ(19), IDI48_REGMAP_IRQ(20), /* 18-20 */
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IDI48_REGMAP_IRQ(21), IDI48_REGMAP_IRQ(22), IDI48_REGMAP_IRQ(23), /* 21-23 */
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IDI48_REGMAP_IRQ(24), IDI48_REGMAP_IRQ(25), IDI48_REGMAP_IRQ(26), /* 24-26 */
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IDI48_REGMAP_IRQ(27), IDI48_REGMAP_IRQ(28), IDI48_REGMAP_IRQ(29), /* 27-29 */
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IDI48_REGMAP_IRQ(30), IDI48_REGMAP_IRQ(31), IDI48_REGMAP_IRQ(32), /* 30-32 */
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IDI48_REGMAP_IRQ(33), IDI48_REGMAP_IRQ(34), IDI48_REGMAP_IRQ(35), /* 33-35 */
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IDI48_REGMAP_IRQ(36), IDI48_REGMAP_IRQ(37), IDI48_REGMAP_IRQ(38), /* 36-38 */
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IDI48_REGMAP_IRQ(39), IDI48_REGMAP_IRQ(40), IDI48_REGMAP_IRQ(41), /* 39-41 */
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IDI48_REGMAP_IRQ(42), IDI48_REGMAP_IRQ(43), IDI48_REGMAP_IRQ(44), /* 42-44 */
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IDI48_REGMAP_IRQ(45), IDI48_REGMAP_IRQ(46), IDI48_REGMAP_IRQ(47), /* 45-47 */
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};
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static const char *idi48_names[IDI48_NGPIO] = {
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"Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
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"Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
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@ -228,22 +164,14 @@ static const char *idi48_names[IDI48_NGPIO] = {
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"Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
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};
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static int idi_48_irq_init_hw(struct gpio_chip *gc)
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{
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struct idi_48_gpio *const idi48gpio = gpiochip_get_data(gc);
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/* Disable IRQ by default */
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iowrite8(0, &idi48gpio->reg->irq);
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ioread8(&idi48gpio->reg->irq);
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return 0;
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}
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static int idi_48_probe(struct device *dev, unsigned int id)
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{
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struct idi_48_gpio *idi48gpio;
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const char *const name = dev_name(dev);
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struct gpio_irq_chip *girq;
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void __iomem *regs;
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struct regmap *map;
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struct regmap_irq_chip *chip;
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struct regmap_irq_chip_data *chip_data;
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int err;
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idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
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@ -256,9 +184,32 @@ static int idi_48_probe(struct device *dev, unsigned int id)
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return -EBUSY;
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}
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idi48gpio->reg = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
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if (!idi48gpio->reg)
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regs = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
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if (!regs)
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return -ENOMEM;
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idi48gpio->reg = regs;
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map = devm_regmap_init_mmio(dev, regs, &idi48_regmap_config);
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if (IS_ERR(map))
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return dev_err_probe(dev, PTR_ERR(map),
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"Unable to initialize register map\n");
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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chip->name = name;
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chip->status_base = IDI48_IRQ_STATUS;
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chip->unmask_base = IDI48_IRQ_ENABLE;
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chip->clear_on_unmask = true;
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chip->num_regs = 1;
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chip->irqs = idi48_regmap_irqs;
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chip->num_irqs = ARRAY_SIZE(idi48_regmap_irqs);
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err = devm_regmap_add_irq_chip(dev, map, irq[id], IRQF_SHARED, 0, chip,
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&chip_data);
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if (err)
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return dev_err_probe(dev, err, "IRQ registration failed\n");
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idi48gpio->chip.label = name;
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idi48gpio->chip.parent = dev;
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@ -271,32 +222,14 @@ static int idi_48_probe(struct device *dev, unsigned int id)
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idi48gpio->chip.get = idi_48_gpio_get;
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idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple;
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girq = &idi48gpio->chip.irq;
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gpio_irq_chip_set_chip(girq, &idi_48_irqchip);
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/* This will let us handle the parent IRQ in the driver */
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girq->parent_handler = NULL;
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_edge_irq;
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girq->init_hw = idi_48_irq_init_hw;
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spin_lock_init(&idi48gpio->lock);
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err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
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if (err) {
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dev_err(dev, "GPIO registering failed (%d)\n", err);
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return err;
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}
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err = devm_request_irq(dev, irq[id], idi_48_irq_handler, IRQF_SHARED,
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name, idi48gpio);
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if (err) {
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dev_err(dev, "IRQ handler registering failed (%d)\n", err);
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return err;
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}
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return 0;
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return gpiochip_irqchip_add_domain(&idi48gpio->chip,
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regmap_irq_get_domain(chip_data));
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}
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static struct isa_driver idi_48_driver = {
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