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iio: accel: adxl367: Fix alignment for DMA safety

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____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_DMA_MINALIGN definition.

Update comment to reflect that DMA safety may require separate
cachelines.

Fixes: cbab791c5e ("iio: accel: add ADXL367 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <demonsingur@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-5-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:55:44 +01:00
parent 46403dcf3a
commit e1f956a804
2 changed files with 6 additions and 4 deletions
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2
drivers/iio/accel/adxl367.c
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@ -179,7 +179,7 @@ struct adxl367_state {
unsigned int fifo_set_size;
unsigned int fifo_watermark;
__be16 fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned;
__be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
__be16 sample_buf;
u8 act_threshold_buf[2];
u8 inact_time_buf[2];

8
drivers/iio/accel/adxl367_spi.c
View File

@ -9,6 +9,8 @@
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include "adxl367.h"
#define ADXL367_SPI_WRITE_COMMAND 0x0A
@ -28,10 +30,10 @@ struct adxl367_spi_state {
struct spi_transfer fifo_xfer[2];
/*
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
* DMA (thus cache coherency maintenance) may require the
* transfer buffers live in their own cache lines.
*/
u8 reg_write_tx_buf[1] ____cacheline_aligned;
u8 reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN);
u8 reg_read_tx_buf[2];
u8 fifo_tx_buf[1];
};