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S5P: SYSMMU: Remove System MMU device driver
This patch removes System MMU device driver from arm/plat-s5p tree for transition to implement IOMMU driver. Although controlling System MMU in this removing driver is similar to the new IOMMU driver in the following patch, the new one is almost rewrite of this driver and there is no benefit to moving the driver file from arch/arm/ to drivers/iommu. Signed-off-by: KyongHo Cho <pullip.cho@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
KyongHo Cho
Kukjin Kim
parent
dd775ae254
commit
e1f80f5744
@ -50,14 +50,6 @@ config S5P_PM
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Common code for power management support on S5P and newer SoCs
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Note: Do not select this for S5P6440 and S5P6450.
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comment "System MMU"
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config S5P_SYSTEM_MMU
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bool "S5P SYSTEM MMU"
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depends on ARCH_EXYNOS4
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help
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Say Y here if you want to enable System MMU
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config S5P_SLEEP
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bool
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help
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@ -16,7 +16,6 @@ obj-y += clock.o
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obj-y += irq.o
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obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
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obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
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obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o
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obj-$(CONFIG_S5P_PM) += pm.o irq-pm.o
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obj-$(CONFIG_S5P_SLEEP) += sleep.o
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obj-$(CONFIG_S5P_HRT) += s5p-time.o
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@ -1,313 +0,0 @@
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/* linux/arch/arm/plat-s5p/sysmmu.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/export.h>
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#include <asm/pgtable.h>
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#include <mach/map.h>
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#include <mach/regs-sysmmu.h>
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#include <plat/sysmmu.h>
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#define CTRL_ENABLE 0x5
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#define CTRL_BLOCK 0x7
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#define CTRL_DISABLE 0x0
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static struct device *dev;
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static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
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S5P_PAGE_FAULT_ADDR,
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S5P_AR_FAULT_ADDR,
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S5P_AW_FAULT_ADDR,
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S5P_DEFAULT_SLAVE_ADDR,
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S5P_AR_FAULT_ADDR,
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S5P_AR_FAULT_ADDR,
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S5P_AW_FAULT_ADDR,
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S5P_AW_FAULT_ADDR
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};
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static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
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"PAGE FAULT",
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"AR MULTI-HIT FAULT",
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"AW MULTI-HIT FAULT",
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"BUS ERROR",
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"AR SECURITY PROTECTION FAULT",
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"AR ACCESS PROTECTION FAULT",
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"AW SECURITY PROTECTION FAULT",
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"AW ACCESS PROTECTION FAULT"
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};
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static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
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enum S5P_SYSMMU_INTERRUPT_TYPE itype,
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unsigned long pgtable_base,
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unsigned long fault_addr);
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/*
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* If adjacent 2 bits are true, the system MMU is enabled.
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* The system MMU is disabled, otherwise.
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*/
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static unsigned long sysmmu_states;
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static inline void set_sysmmu_active(sysmmu_ips ips)
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{
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sysmmu_states |= 3 << (ips * 2);
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}
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static inline void set_sysmmu_inactive(sysmmu_ips ips)
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{
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sysmmu_states &= ~(3 << (ips * 2));
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}
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static inline int is_sysmmu_active(sysmmu_ips ips)
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{
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return sysmmu_states & (3 << (ips * 2));
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}
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static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
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static inline void sysmmu_block(sysmmu_ips ips)
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{
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__raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
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dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
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}
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static inline void sysmmu_unblock(sysmmu_ips ips)
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{
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__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
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dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
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}
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static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
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{
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__raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
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dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
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}
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static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
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{
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if (unlikely(pgd == 0)) {
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pgd = (unsigned long)ZERO_PAGE(0);
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__raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
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} else {
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__raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
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}
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__raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
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dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
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sysmmu_ips_name[ips], pgd);
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__sysmmu_tlb_invalidate(ips);
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}
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void sysmmu_set_fault_handler(sysmmu_ips ips,
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int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
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unsigned long pgtable_base,
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unsigned long fault_addr))
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{
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BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
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fault_handlers[ips] = handler;
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}
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static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
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{
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/* SYSMMU is in blocked when interrupt occurred. */
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unsigned long base = 0;
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sysmmu_ips ips = (sysmmu_ips)dev_id;
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enum S5P_SYSMMU_INTERRUPT_TYPE itype;
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itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
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__ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
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BUG_ON(!((itype >= 0) && (itype < 8)));
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dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
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sysmmu_ips_name[ips]);
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if (fault_handlers[ips]) {
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unsigned long addr;
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base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
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addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
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if (fault_handlers[ips](itype, base, addr)) {
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__raw_writel(1 << itype,
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sysmmusfrs[ips] + S5P_INT_CLEAR);
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dev_notice(dev, "%s from %s is resolved."
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" Retrying translation.\n",
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sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
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} else {
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base = 0;
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}
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}
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sysmmu_unblock(ips);
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if (!base)
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dev_notice(dev, "%s from %s is not handled.\n",
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sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
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return IRQ_HANDLED;
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}
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void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
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{
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if (is_sysmmu_active(ips)) {
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sysmmu_block(ips);
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__sysmmu_set_ptbase(ips, pgd);
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sysmmu_unblock(ips);
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} else {
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dev_dbg(dev, "%s is disabled. "
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"Skipping initializing page table base.\n",
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sysmmu_ips_name[ips]);
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}
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}
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void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
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{
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if (!is_sysmmu_active(ips)) {
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sysmmu_clk_enable(ips);
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__sysmmu_set_ptbase(ips, pgd);
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__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
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set_sysmmu_active(ips);
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dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
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} else {
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dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
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}
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}
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void s5p_sysmmu_disable(sysmmu_ips ips)
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{
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if (is_sysmmu_active(ips)) {
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__raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
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set_sysmmu_inactive(ips);
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sysmmu_clk_disable(ips);
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dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
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} else {
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dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
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}
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}
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void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
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{
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if (is_sysmmu_active(ips)) {
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sysmmu_block(ips);
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__sysmmu_tlb_invalidate(ips);
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sysmmu_unblock(ips);
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} else {
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dev_dbg(dev, "%s is disabled. "
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"Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
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}
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}
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static int s5p_sysmmu_probe(struct platform_device *pdev)
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{
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int i, ret;
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struct resource *res, *mem;
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dev = &pdev->dev;
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for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
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int irq;
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sysmmu_clk_init(dev, i);
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sysmmu_clk_disable(i);
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res) {
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dev_err(dev, "Failed to get the resource of %s.\n",
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sysmmu_ips_name[i]);
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ret = -ENODEV;
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goto err_res;
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}
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mem = request_mem_region(res->start, resource_size(res),
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pdev->name);
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if (!mem) {
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dev_err(dev, "Failed to request the memory region of %s.\n",
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sysmmu_ips_name[i]);
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ret = -EBUSY;
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goto err_res;
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}
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sysmmusfrs[i] = ioremap(res->start, resource_size(res));
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if (!sysmmusfrs[i]) {
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dev_err(dev, "Failed to ioremap() for %s.\n",
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sysmmu_ips_name[i]);
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ret = -ENXIO;
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goto err_reg;
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}
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irq = platform_get_irq(pdev, i);
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if (irq <= 0) {
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dev_err(dev, "Failed to get the IRQ resource of %s.\n",
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sysmmu_ips_name[i]);
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ret = -ENOENT;
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goto err_map;
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}
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if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
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pdev->name, (void *)i)) {
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dev_err(dev, "Failed to request IRQ for %s.\n",
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sysmmu_ips_name[i]);
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ret = -ENOENT;
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goto err_map;
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}
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}
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return 0;
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err_map:
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iounmap(sysmmusfrs[i]);
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err_reg:
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release_mem_region(mem->start, resource_size(mem));
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err_res:
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return ret;
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}
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static int s5p_sysmmu_remove(struct platform_device *pdev)
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{
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return 0;
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}
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int s5p_sysmmu_runtime_suspend(struct device *dev)
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{
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return 0;
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}
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int s5p_sysmmu_runtime_resume(struct device *dev)
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{
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return 0;
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}
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const struct dev_pm_ops s5p_sysmmu_pm_ops = {
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.runtime_suspend = s5p_sysmmu_runtime_suspend,
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.runtime_resume = s5p_sysmmu_runtime_resume,
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};
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static struct platform_driver s5p_sysmmu_driver = {
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.probe = s5p_sysmmu_probe,
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.remove = s5p_sysmmu_remove,
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.driver = {
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.owner = THIS_MODULE,
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.name = "s5p-sysmmu",
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.pm = &s5p_sysmmu_pm_ops,
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}
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};
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static int __init s5p_sysmmu_init(void)
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{
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return platform_driver_register(&s5p_sysmmu_driver);
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}
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arch_initcall(s5p_sysmmu_init);
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@ -133,7 +133,6 @@ extern struct platform_device exynos4_device_pcm1;
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extern struct platform_device exynos4_device_pcm2;
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extern struct platform_device exynos4_device_pd[];
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extern struct platform_device exynos4_device_spdif;
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extern struct platform_device exynos4_device_sysmmu;
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extern struct platform_device samsung_asoc_dma;
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extern struct platform_device samsung_asoc_idma;
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@ -1,95 +0,0 @@
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/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung System MMU driver for S5P platform
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_SAMSUNG_SYSMMU_H
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#define __PLAT_SAMSUNG_SYSMMU_H __FILE__
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enum S5P_SYSMMU_INTERRUPT_TYPE {
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SYSMMU_PAGEFAULT,
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SYSMMU_AR_MULTIHIT,
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SYSMMU_AW_MULTIHIT,
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SYSMMU_BUSERROR,
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SYSMMU_AR_SECURITY,
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SYSMMU_AR_ACCESS,
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SYSMMU_AW_SECURITY,
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SYSMMU_AW_PROTECTION, /* 7 */
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SYSMMU_FAULTS_NUM
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};
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#ifdef CONFIG_S5P_SYSTEM_MMU
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#include <mach/sysmmu.h>
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/**
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* s5p_sysmmu_enable() - enable system mmu of ip
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* @ips: The ip connected system mmu.
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* #pgd: Base physical address of the 1st level page table
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*
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* This function enable system mmu to transfer address
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* from virtual address to physical address
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*/
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void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
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/**
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* s5p_sysmmu_disable() - disable sysmmu mmu of ip
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* @ips: The ip connected system mmu.
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*
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* This function disable system mmu to transfer address
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* from virtual address to physical address
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*/
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void s5p_sysmmu_disable(sysmmu_ips ips);
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/**
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* s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
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* @ips: The ip connected system mmu.
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* @pgd: The page table base address.
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*
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* This function set page table base address
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* When system mmu transfer address from virtaul address to physical address,
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* system mmu refer address information from page table
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*/
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void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
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/**
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* s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
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* @ips: The ip connected system mmu.
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*
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* This function flush all TLB entry in system mmu
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*/
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void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
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/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
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* @itype: type of fault.
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* @pgtable_base: the physical address of page table base. This is 0 if @ips is
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* SYSMMU_BUSERROR.
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* @fault_addr: the device (virtual) address that the System MMU tried to
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* translated. This is 0 if @ips is SYSMMU_BUSERROR.
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* Called when interrupt occurred by the System MMUs
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* The device drivers of peripheral devices that has a System MMU can implement
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* a fault handler to resolve address translation fault by System MMU.
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* The meanings of return value and parameters are described below.
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* return value: non-zero if the fault is correctly resolved.
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* zero if the fault is not handled.
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*/
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void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
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int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
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unsigned long pgtable_base,
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unsigned long fault_addr));
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#else
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#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
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#define s5p_sysmmu_disable(ips) do { } while (0)
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#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
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#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
|
||||
#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
|
||||
#endif
|
||||
#endif /* __ASM_PLAT_SYSMMU_H */
|
||||
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Reference in New Issue
Block a user