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imx-drm: fixes for parallel-display, imx-tve, and ipu-common

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These patches fix the parallel-display driver to use the standard OF
 graph bindings for connecting a drm_panel via device tree instead of
 an undocumented, driver specific device tree property, take care to
 disable all IPU interrupts before setting up the irq chip to fix a
 kexec lockup, and fix VGA output on i.MX53-QSB boards by correcting
 the media bus format set by the imx-tve driver.
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Merge tag 'imx-drm-fixes-2015-07-14' of git://git.pengutronix.de/git/pza/linux into drm-fixes

imx-drm: fixes for parallel-display, imx-tve, and ipu-common

These patches fix the parallel-display driver to use the standard OF
graph bindings for connecting a drm_panel via device tree instead of
an undocumented, driver specific device tree property, take care to
disable all IPU interrupts before setting up the irq chip to fix a
kexec lockup, and fix VGA output on i.MX53-QSB boards by correcting
the media bus format set by the imx-tve driver.

* tag 'imx-drm-fixes-2015-07-14' of git://git.pengutronix.de/git/pza/linux:
  drm/imx: tve: fix media bus format for VGA output
  GPU: ipu: fix lockup caused by pending chained interrupts
  drm/imx: parallel-display: fix drm_panel support
This commit is contained in:
Dave Airlie 2015-07-17 10:24:34 +10:00
commit e1e50e1e1e
4 changed files with 43 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
Documentation/devicetree/bindings/drm/imx/fsl-imx-drm.txt
View File

@ -65,8 +65,10 @@ Optional properties:
- edid: verbatim EDID data block describing attached display.
- ddc: phandle describing the i2c bus handling the display data
channel
- port: A port node with endpoint definitions as defined in
- port@[0-1]: Port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Port 0 is the input port connected to the IPU display interface,
port 1 is the output port connected to a panel.
example:
@ -75,9 +77,29 @@ display@di0 {
edid = [edid-data];
interface-pix-fmt = "rgb24";
port {
port@0 {
reg = <0>;
display_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
port@1 {
reg = <1>;
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
panel {
...
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};

2
drivers/gpu/drm/imx/imx-tve.c
View File

@ -301,7 +301,7 @@ static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
switch (tve->mode) {
case TVE_MODE_VGA:
imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_YUV8_1X24,
imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_GBR888_1X24,
tve->hsync_pin, tve->vsync_pin);
break;
case TVE_MODE_TVOUT:

21
drivers/gpu/drm/imx/parallel-display.c
View File

@ -21,6 +21,7 @@
#include <drm/drm_panel.h>
#include <linux/videodev2.h>
#include <video/of_display_timing.h>
#include <linux/of_graph.h>
#include "imx-drm.h"
@ -208,7 +209,7 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
{
struct drm_device *drm = data;
struct device_node *np = dev->of_node;
struct device_node *panel_node;
struct device_node *port;
const u8 *edidp;
struct imx_parallel_display *imxpd;
int ret;
@ -234,11 +235,19 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
imxpd->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
}
panel_node = of_parse_phandle(np, "fsl,panel", 0);
if (panel_node) {
imxpd->panel = of_drm_find_panel(panel_node);
if (!imxpd->panel)
return -EPROBE_DEFER;
/* port@1 is the output port */
port = of_graph_get_port_by_id(np, 1);
if (port) {
struct device_node *endpoint, *remote;
endpoint = of_get_child_by_name(port, "endpoint");
if (endpoint) {
remote = of_graph_get_remote_port_parent(endpoint);
if (remote)
imxpd->panel = of_drm_find_panel(remote);
if (!imxpd->panel)
return -EPROBE_DEFER;
}
}
imxpd->dev = dev;

3
drivers/gpu/ipu-v3/ipu-common.c
View File

@ -1107,6 +1107,9 @@ static int ipu_irq_init(struct ipu_soc *ipu)
return ret;
}
for (i = 0; i < IPU_NUM_IRQS; i += 32)
ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
for (i = 0; i < IPU_NUM_IRQS; i += 32) {
gc = irq_get_domain_generic_chip(ipu->domain, i);
gc->reg_base = ipu->cm_reg;