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usb: isp1760: Reorganize header files
The isp1760-rhcd.h header contains PTD constants and structures only useful for the HCD implementation. It also contains register definitions that will be needed by common code when implementing support for the ISP1761 device controller, but doesn't contain the isp1760_hcd structure definition that will also be used by common code. Move definitions to the right location and create an isp1760-regs.h to store register definitions. No change other than moving definitions and modifying indentation is performed. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Laurent Pinchart
Felipe Balbi
parent
ea0b1fabc7
commit
e19c99e759
@ -27,41 +27,12 @@
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#include <asm/cacheflush.h>
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#include "isp1760-hcd.h"
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#include "isp1760-regs.h"
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static struct kmem_cache *qtd_cachep;
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static struct kmem_cache *qh_cachep;
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static struct kmem_cache *urb_listitem_cachep;
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enum queue_head_types {
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QH_CONTROL,
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QH_BULK,
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QH_INTERRUPT,
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QH_END
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};
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struct isp1760_hcd {
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struct usb_hcd *hcd;
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u32 hcs_params;
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spinlock_t lock;
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struct isp1760_slotinfo atl_slots[32];
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int atl_done_map;
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struct isp1760_slotinfo int_slots[32];
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int int_done_map;
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struct isp1760_memory_chunk memory_pool[BLOCKS];
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struct list_head qh_list[QH_END];
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/* periodic schedule support */
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#define DEFAULT_I_TDPS 1024
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unsigned periodic_size;
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unsigned i_thresh;
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unsigned long reset_done;
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unsigned long next_statechange;
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unsigned int devflags;
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struct gpio_desc *rst_gpio;
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};
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typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
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struct isp1760_qtd *qtd);
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@ -70,32 +41,79 @@ static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
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return *(struct isp1760_hcd **)hcd->hcd_priv;
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}
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/* Section 2.2 Host Controller Capability Registers */
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#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
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#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
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#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
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#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
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#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
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#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
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#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
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/* urb state*/
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#define DELETE_URB (0x0008)
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#define NO_TRANSFER_ACTIVE (0xffffffff)
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/* Section 2.3 Host Controller Operational Registers */
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#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
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#define CMD_RESET (1<<1) /* reset HC not bus */
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#define CMD_RUN (1<<0) /* start/stop HC */
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#define STS_PCD (1<<2) /* port change detect */
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#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
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/* Philips Proprietary Transfer Descriptor (PTD) */
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typedef __u32 __bitwise __dw;
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struct ptd {
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__dw dw0;
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__dw dw1;
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__dw dw2;
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__dw dw3;
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__dw dw4;
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__dw dw5;
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__dw dw6;
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__dw dw7;
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};
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#define PTD_OFFSET 0x0400
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#define ISO_PTD_OFFSET 0x0400
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#define INT_PTD_OFFSET 0x0800
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#define ATL_PTD_OFFSET 0x0c00
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#define PAYLOAD_OFFSET 0x1000
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#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
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#define PORT_POWER (1<<12) /* true: has power (see PPC) */
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#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
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#define PORT_RESET (1<<8) /* reset port */
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#define PORT_SUSPEND (1<<7) /* suspend port */
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#define PORT_RESUME (1<<6) /* resume it */
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#define PORT_PE (1<<2) /* port enable */
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#define PORT_CSC (1<<1) /* connect status change */
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#define PORT_CONNECT (1<<0) /* device connected */
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#define PORT_RWC_BITS (PORT_CSC)
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/* ATL */
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/* DW0 */
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#define DW0_VALID_BIT 1
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#define FROM_DW0_VALID(x) ((x) & 0x01)
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#define TO_DW0_LENGTH(x) (((u32) x) << 3)
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#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
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#define TO_DW0_MULTI(x) (((u32) x) << 29)
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#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
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/* DW1 */
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#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
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#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
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#define DW1_TRANS_BULK ((u32) 2 << 12)
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#define DW1_TRANS_INT ((u32) 3 << 12)
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#define DW1_TRANS_SPLIT ((u32) 1 << 14)
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#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
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#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
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#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
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/* DW2 */
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#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
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#define TO_DW2_RL(x) ((x) << 25)
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#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
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/* DW3 */
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#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
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#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
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#define TO_DW3_NAKCOUNT(x) ((x) << 19)
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#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
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#define TO_DW3_CERR(x) ((x) << 23)
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#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
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#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
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#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
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#define TO_DW3_PING(x) ((x) << 26)
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#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
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#define DW3_ERROR_BIT (1 << 28)
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#define DW3_BABBLE_BIT (1 << 29)
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#define DW3_HALT_BIT (1 << 30)
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#define DW3_ACTIVE_BIT (1 << 31)
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#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
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#define INT_UNDERRUN (1 << 2)
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#define INT_BABBLE (1 << 1)
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#define INT_EXACT (1 << 0)
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#define SETUP_PID (2)
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#define IN_PID (1)
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#define OUT_PID (0)
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/* Errata 1 */
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#define RL_COUNTER (0)
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#define NAK_COUNTER (0)
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#define ERR_COUNTER (2)
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struct isp1760_qtd {
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u8 packet_type;
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@ -1,135 +1,13 @@
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#ifndef _ISP1760_HCD_H_
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#define _ISP1760_HCD_H_
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/* exports for if */
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int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
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struct device *dev, unsigned int devflags);
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void isp1760_unregister(struct device *dev);
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#include <linux/spinlock.h>
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int isp1760_init_kmem_once(void);
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void isp1760_deinit_kmem_cache(void);
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/* EHCI capability registers */
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#define HC_CAPLENGTH 0x00
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#define HC_HCSPARAMS 0x04
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#define HC_HCCPARAMS 0x08
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/* EHCI operational registers */
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#define HC_USBCMD 0x20
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#define HC_USBSTS 0x24
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#define HC_FRINDEX 0x2c
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#define HC_CONFIGFLAG 0x60
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#define HC_PORTSC1 0x64
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#define HC_ISO_PTD_DONEMAP_REG 0x130
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#define HC_ISO_PTD_SKIPMAP_REG 0x134
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#define HC_ISO_PTD_LASTPTD_REG 0x138
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#define HC_INT_PTD_DONEMAP_REG 0x140
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#define HC_INT_PTD_SKIPMAP_REG 0x144
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#define HC_INT_PTD_LASTPTD_REG 0x148
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#define HC_ATL_PTD_DONEMAP_REG 0x150
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#define HC_ATL_PTD_SKIPMAP_REG 0x154
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#define HC_ATL_PTD_LASTPTD_REG 0x158
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/* Configuration Register */
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#define HC_HW_MODE_CTRL 0x300
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#define ALL_ATX_RESET (1 << 31)
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#define HW_ANA_DIGI_OC (1 << 15)
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#define HW_DATA_BUS_32BIT (1 << 8)
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#define HW_DACK_POL_HIGH (1 << 6)
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#define HW_DREQ_POL_HIGH (1 << 5)
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#define HW_INTR_HIGH_ACT (1 << 2)
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#define HW_INTR_EDGE_TRIG (1 << 1)
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#define HW_GLOBAL_INTR_EN (1 << 0)
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#define HC_CHIP_ID_REG 0x304
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#define HC_SCRATCH_REG 0x308
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#define HC_RESET_REG 0x30c
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#define SW_RESET_RESET_HC (1 << 1)
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#define SW_RESET_RESET_ALL (1 << 0)
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#define HC_BUFFER_STATUS_REG 0x334
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#define ISO_BUF_FILL (1 << 2)
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#define INT_BUF_FILL (1 << 1)
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#define ATL_BUF_FILL (1 << 0)
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#define HC_MEMORY_REG 0x33c
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#define ISP_BANK(x) ((x) << 16)
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#define HC_PORT1_CTRL 0x374
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#define PORT1_POWER (3 << 3)
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#define PORT1_INIT1 (1 << 7)
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#define PORT1_INIT2 (1 << 23)
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#define HW_OTG_CTRL_SET 0x374
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#define HW_OTG_CTRL_CLR 0x376
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/* Interrupt Register */
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#define HC_INTERRUPT_REG 0x310
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#define HC_INTERRUPT_ENABLE 0x314
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#define HC_ISO_INT (1 << 9)
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#define HC_ATL_INT (1 << 8)
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#define HC_INTL_INT (1 << 7)
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#define HC_EOT_INT (1 << 3)
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#define HC_SOT_INT (1 << 1)
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#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
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#define HC_ISO_IRQ_MASK_OR_REG 0x318
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#define HC_INT_IRQ_MASK_OR_REG 0x31C
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#define HC_ATL_IRQ_MASK_OR_REG 0x320
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#define HC_ISO_IRQ_MASK_AND_REG 0x324
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#define HC_INT_IRQ_MASK_AND_REG 0x328
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#define HC_ATL_IRQ_MASK_AND_REG 0x32C
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/* urb state*/
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#define DELETE_URB (0x0008)
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#define NO_TRANSFER_ACTIVE (0xffffffff)
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/* Philips Proprietary Transfer Descriptor (PTD) */
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typedef __u32 __bitwise __dw;
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struct ptd {
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__dw dw0;
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__dw dw1;
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__dw dw2;
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__dw dw3;
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__dw dw4;
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__dw dw5;
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__dw dw6;
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__dw dw7;
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};
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#define PTD_OFFSET 0x0400
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#define ISO_PTD_OFFSET 0x0400
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#define INT_PTD_OFFSET 0x0800
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#define ATL_PTD_OFFSET 0x0c00
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#define PAYLOAD_OFFSET 0x1000
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struct isp1760_slotinfo {
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struct isp1760_qh *qh;
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struct isp1760_qtd *qtd;
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unsigned long timestamp;
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};
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/*
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* Device flags that can vary from board to board. All of these
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* indicate the most "atypical" case, so that a devflags of 0 is
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* a sane default configuration.
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*/
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#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
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#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
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#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
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#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
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#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
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#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
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#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
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#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
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/* chip memory management */
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struct isp1760_memory_chunk {
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unsigned int start;
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unsigned int size;
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unsigned int free;
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};
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struct gpio_desc;
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struct isp1760_qh;
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struct isp1760_qtd;
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struct resource;
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struct usb_hcd;
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/*
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* 60kb divided in:
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@ -149,55 +27,69 @@ struct isp1760_memory_chunk {
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#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
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#define PAYLOAD_AREA_SIZE 0xf000
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/* ATL */
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/* DW0 */
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#define DW0_VALID_BIT 1
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#define FROM_DW0_VALID(x) ((x) & 0x01)
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#define TO_DW0_LENGTH(x) (((u32) x) << 3)
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#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
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#define TO_DW0_MULTI(x) (((u32) x) << 29)
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#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
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/* DW1 */
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#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
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#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
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#define DW1_TRANS_BULK ((u32) 2 << 12)
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#define DW1_TRANS_INT ((u32) 3 << 12)
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#define DW1_TRANS_SPLIT ((u32) 1 << 14)
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#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
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#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
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#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
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/* DW2 */
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#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
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#define TO_DW2_RL(x) ((x) << 25)
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#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
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/* DW3 */
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#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
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#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
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#define TO_DW3_NAKCOUNT(x) ((x) << 19)
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#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
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#define TO_DW3_CERR(x) ((x) << 23)
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#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
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#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
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#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
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#define TO_DW3_PING(x) ((x) << 26)
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#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
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#define DW3_ERROR_BIT (1 << 28)
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#define DW3_BABBLE_BIT (1 << 29)
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#define DW3_HALT_BIT (1 << 30)
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#define DW3_ACTIVE_BIT (1 << 31)
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#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
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/*
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* Device flags that can vary from board to board. All of these
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* indicate the most "atypical" case, so that a devflags of 0 is
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* a sane default configuration.
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*/
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#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
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#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
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#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
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#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
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#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
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#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
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#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
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#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
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#define INT_UNDERRUN (1 << 2)
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#define INT_BABBLE (1 << 1)
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#define INT_EXACT (1 << 0)
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struct isp1760_slotinfo {
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struct isp1760_qh *qh;
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struct isp1760_qtd *qtd;
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unsigned long timestamp;
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};
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#define SETUP_PID (2)
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#define IN_PID (1)
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#define OUT_PID (0)
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/* chip memory management */
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struct isp1760_memory_chunk {
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unsigned int start;
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unsigned int size;
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unsigned int free;
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};
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/* Errata 1 */
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#define RL_COUNTER (0)
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#define NAK_COUNTER (0)
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#define ERR_COUNTER (2)
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enum isp1760_queue_head_types {
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QH_CONTROL,
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QH_BULK,
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QH_INTERRUPT,
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QH_END
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};
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struct isp1760_hcd {
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struct usb_hcd *hcd;
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u32 hcs_params;
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spinlock_t lock;
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struct isp1760_slotinfo atl_slots[32];
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int atl_done_map;
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struct isp1760_slotinfo int_slots[32];
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int int_done_map;
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struct isp1760_memory_chunk memory_pool[BLOCKS];
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struct list_head qh_list[QH_END];
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/* periodic schedule support */
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#define DEFAULT_I_TDPS 1024
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unsigned periodic_size;
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unsigned i_thresh;
|
||||
unsigned long reset_done;
|
||||
unsigned long next_statechange;
|
||||
unsigned int devflags;
|
||||
|
||||
struct gpio_desc *rst_gpio;
|
||||
};
|
||||
|
||||
/* exports for if */
|
||||
int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
|
||||
struct device *dev, unsigned int devflags);
|
||||
void isp1760_unregister(struct device *dev);
|
||||
|
||||
int isp1760_init_kmem_once(void);
|
||||
void isp1760_deinit_kmem_cache(void);
|
||||
|
||||
#endif /* _ISP1760_HCD_H_ */
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include <linux/usb/hcd.h>
|
||||
|
||||
#include "isp1760-hcd.h"
|
||||
#include "isp1760-regs.h"
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#include <linux/pci.h>
|
||||
|
||||
120
drivers/usb/host/isp1760-regs.h
Normal file
120
drivers/usb/host/isp1760-regs.h
Normal file
@ -0,0 +1,120 @@
|
||||
/*
|
||||
* Driver for the NXP ISP1760 chip
|
||||
*
|
||||
* Copyright 2014 Laurent Pinchart
|
||||
* Copyright 2007 Sebastian Siewior
|
||||
*
|
||||
* Contacts:
|
||||
* Sebastian Siewior <bigeasy@linutronix.de>
|
||||
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _ISP1760_REGS_H_
|
||||
#define _ISP1760_REGS_H_
|
||||
|
||||
/* EHCI capability registers */
|
||||
#define HC_CAPLENGTH 0x000
|
||||
#define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */
|
||||
#define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */
|
||||
|
||||
#define HC_HCSPARAMS 0x004
|
||||
#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */
|
||||
#define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */
|
||||
#define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
|
||||
|
||||
#define HC_HCCPARAMS 0x008
|
||||
#define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */
|
||||
#define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
|
||||
|
||||
/* EHCI operational registers */
|
||||
#define HC_USBCMD 0x020
|
||||
#define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */
|
||||
#define CMD_RESET (1 << 1) /* reset HC not bus */
|
||||
#define CMD_RUN (1 << 0) /* start/stop HC */
|
||||
|
||||
#define HC_USBSTS 0x024
|
||||
#define STS_PCD (1 << 2) /* port change detect */
|
||||
|
||||
#define HC_FRINDEX 0x02c
|
||||
|
||||
#define HC_CONFIGFLAG 0x060
|
||||
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
|
||||
|
||||
#define HC_PORTSC1 0x064
|
||||
#define PORT_OWNER (1 << 13) /* true: companion hc owns this port */
|
||||
#define PORT_POWER (1 << 12) /* true: has power (see PPC) */
|
||||
#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
|
||||
#define PORT_RESET (1 << 8) /* reset port */
|
||||
#define PORT_SUSPEND (1 << 7) /* suspend port */
|
||||
#define PORT_RESUME (1 << 6) /* resume it */
|
||||
#define PORT_PE (1 << 2) /* port enable */
|
||||
#define PORT_CSC (1 << 1) /* connect status change */
|
||||
#define PORT_CONNECT (1 << 0) /* device connected */
|
||||
#define PORT_RWC_BITS (PORT_CSC)
|
||||
|
||||
#define HC_ISO_PTD_DONEMAP_REG 0x130
|
||||
#define HC_ISO_PTD_SKIPMAP_REG 0x134
|
||||
#define HC_ISO_PTD_LASTPTD_REG 0x138
|
||||
#define HC_INT_PTD_DONEMAP_REG 0x140
|
||||
#define HC_INT_PTD_SKIPMAP_REG 0x144
|
||||
#define HC_INT_PTD_LASTPTD_REG 0x148
|
||||
#define HC_ATL_PTD_DONEMAP_REG 0x150
|
||||
#define HC_ATL_PTD_SKIPMAP_REG 0x154
|
||||
#define HC_ATL_PTD_LASTPTD_REG 0x158
|
||||
|
||||
/* Configuration Register */
|
||||
#define HC_HW_MODE_CTRL 0x300
|
||||
#define ALL_ATX_RESET (1 << 31)
|
||||
#define HW_ANA_DIGI_OC (1 << 15)
|
||||
#define HW_DATA_BUS_32BIT (1 << 8)
|
||||
#define HW_DACK_POL_HIGH (1 << 6)
|
||||
#define HW_DREQ_POL_HIGH (1 << 5)
|
||||
#define HW_INTR_HIGH_ACT (1 << 2)
|
||||
#define HW_INTR_EDGE_TRIG (1 << 1)
|
||||
#define HW_GLOBAL_INTR_EN (1 << 0)
|
||||
|
||||
#define HC_CHIP_ID_REG 0x304
|
||||
#define HC_SCRATCH_REG 0x308
|
||||
|
||||
#define HC_RESET_REG 0x30c
|
||||
#define SW_RESET_RESET_HC (1 << 1)
|
||||
#define SW_RESET_RESET_ALL (1 << 0)
|
||||
|
||||
#define HC_BUFFER_STATUS_REG 0x334
|
||||
#define ISO_BUF_FILL (1 << 2)
|
||||
#define INT_BUF_FILL (1 << 1)
|
||||
#define ATL_BUF_FILL (1 << 0)
|
||||
|
||||
#define HC_MEMORY_REG 0x33c
|
||||
#define ISP_BANK(x) ((x) << 16)
|
||||
|
||||
#define HC_PORT1_CTRL 0x374
|
||||
#define PORT1_POWER (3 << 3)
|
||||
#define PORT1_INIT1 (1 << 7)
|
||||
#define PORT1_INIT2 (1 << 23)
|
||||
#define HW_OTG_CTRL_SET 0x374
|
||||
#define HW_OTG_CTRL_CLR 0x376
|
||||
|
||||
/* Interrupt Register */
|
||||
#define HC_INTERRUPT_REG 0x310
|
||||
|
||||
#define HC_INTERRUPT_ENABLE 0x314
|
||||
#define HC_ISO_INT (1 << 9)
|
||||
#define HC_ATL_INT (1 << 8)
|
||||
#define HC_INTL_INT (1 << 7)
|
||||
#define HC_EOT_INT (1 << 3)
|
||||
#define HC_SOT_INT (1 << 1)
|
||||
#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
|
||||
|
||||
#define HC_ISO_IRQ_MASK_OR_REG 0x318
|
||||
#define HC_INT_IRQ_MASK_OR_REG 0x31c
|
||||
#define HC_ATL_IRQ_MASK_OR_REG 0x320
|
||||
#define HC_ISO_IRQ_MASK_AND_REG 0x324
|
||||
#define HC_INT_IRQ_MASK_AND_REG 0x328
|
||||
#define HC_ATL_IRQ_MASK_AND_REG 0x32c
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user