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perf vendor events: Add JSON metrics for imx8mm DDR Perf
Add JSON metrics for imx8mm DDR Perf. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Acked-by: Kajol Jain <kjain@linux.ibm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: John Garry <john.garry@huawei.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Kim Phillips <kim.phillips@amd.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Signed-off-by: John Garry <john.garry@huawei.com> Link: http://lore.kernel.org/lkml/1607080216-36968-11-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -0,0 +1,39 @@
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[
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{
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"BriefDescription": "ddr cycles event",
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"EventCode": "0x00",
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"EventName": "imx8mm_ddr.cycles",
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"Unit": "imx8_ddr",
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"Compat": "i.MX8MM"
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},
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{
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"BriefDescription": "ddr read-cycles event",
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"EventCode": "0x2a",
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"EventName": "imx8mm_ddr.read_cycles",
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"Unit": "imx8_ddr",
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"Compat": "i.MX8MM"
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},
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{
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"BriefDescription": "ddr write-cycles event",
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"EventCode": "0x2b",
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"EventName": "imx8mm_ddr.write_cycles",
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"Unit": "imx8_ddr",
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"Compat": "i.MX8MM"
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},
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{
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"BriefDescription": "ddr read event",
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"EventCode": "0x35",
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"EventName": "imx8mm_ddr.read",
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"Unit": "imx8_ddr",
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"Compat": "i.MX8MM"
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},
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{
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"BriefDescription": "ddr write event",
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"EventCode": "0x38",
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"EventName": "imx8mm_ddr.write",
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"Unit": "imx8_ddr",
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"Compat": "i.MX8MM"
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}
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]
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@ -0,0 +1,18 @@
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[
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{
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"BriefDescription": "bytes all masters read from ddr based on read-cycles event",
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"MetricName": "imx8mm_ddr_read.all",
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"MetricExpr": "imx8mm_ddr.read_cycles * 4 * 4",
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"ScaleUnit": "9.765625e-4KB",
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"Unit": "imx8_ddr",
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"Compat": "i.MX8MM"
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},
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{
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"BriefDescription": "bytes all masters write to ddr based on write-cycles event",
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"MetricName": "imx8mm_ddr_write.all",
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"MetricExpr": "imx8mm_ddr.write_cycles * 4 * 4",
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"ScaleUnit": "9.765625e-4KB",
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"Unit": "imx8_ddr",
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"Compat": "i.MX8MM"
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}
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]
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@ -281,6 +281,8 @@ static struct map {
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{ "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
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{ "hisi_sccl,hha", "hisi_sccl,hha" },
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{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
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/* it's not realistic to keep adding these, we need something more scalable ... */
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{ "imx8_ddr", "imx8_ddr" },
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{ "L3PMC", "amd_l3" },
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{ "DFPMC", "amd_df" },
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{}
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