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scsi: ufs: ufs-mediatek: Add MCQ support for MTK platform
Add UFS MCQ vops and IRQ handler for MediaTek platform. PM flow is fixed accordingly. Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com> Link: https://lore.kernel.org/r/20230701124442.10489-3-powen.kao@mediatek.com Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Po-Wen Kao
Martin K. Petersen
parent
11afb65c10
commit
e152a616c8
@ -27,8 +27,14 @@
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#include <ufs/unipro.h>
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#include "ufs-mediatek.h"
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static int ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq);
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#define CREATE_TRACE_POINTS
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#include "ufs-mediatek-trace.h"
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#undef CREATE_TRACE_POINTS
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#define MAX_SUPP_MAC 64
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#define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200)
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static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
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{ .wmanufacturerid = UFS_ANY_VENDOR,
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@ -840,6 +846,38 @@ static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba)
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}
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}
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static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct platform_device *pdev;
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int i;
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int irq;
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host->mcq_nr_intr = UFSHCD_MAX_Q_NR;
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pdev = container_of(hba->dev, struct platform_device, dev);
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for (i = 0; i < host->mcq_nr_intr; i++) {
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/* irq index 0 is legacy irq, sq/cq irq start from index 1 */
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irq = platform_get_irq(pdev, i + 1);
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if (irq < 0) {
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host->mcq_intr_info[i].irq = MTK_MCQ_INVALID_IRQ;
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dev_err(hba->dev, "get platform mcq irq fail: %d\n", i);
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goto failed;
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}
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host->mcq_intr_info[i].hba = hba;
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host->mcq_intr_info[i].irq = irq;
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dev_info(hba->dev, "get platform mcq irq: %d, %d\n", i, irq);
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}
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return;
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failed:
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/* invalidate irq info */
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for (i = 0; i < host->mcq_nr_intr; i++)
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host->mcq_intr_info[i].irq = MTK_MCQ_INVALID_IRQ;
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host->mcq_nr_intr = 0;
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}
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/**
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* ufs_mtk_init - find other essential mmio bases
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* @hba: host controller instance
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@ -876,6 +914,8 @@ static int ufs_mtk_init(struct ufs_hba *hba)
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/* Initialize host capability */
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ufs_mtk_init_host_caps(hba);
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ufs_mtk_init_mcq_irq(hba);
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err = ufs_mtk_bind_mphy(hba);
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if (err)
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goto out_variant_clear;
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@ -1173,7 +1213,17 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
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else
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return err;
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err = ufshcd_make_hba_operational(hba);
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if (!hba->mcq_enabled) {
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err = ufshcd_make_hba_operational(hba);
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} else {
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ufs_mtk_config_mcq(hba, false);
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ufshcd_mcq_make_queues_operational(hba);
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ufshcd_mcq_config_mac(hba, hba->nutrs);
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/* Enable MCQ mode */
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ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1,
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REG_UFS_MEM_CFG);
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}
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if (err)
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return err;
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@ -1497,6 +1547,121 @@ static int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
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return 0;
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}
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static int ufs_mtk_get_hba_mac(struct ufs_hba *hba)
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{
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return MAX_SUPP_MAC;
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}
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static int ufs_mtk_op_runtime_config(struct ufs_hba *hba)
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{
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struct ufshcd_mcq_opr_info_t *opr;
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int i;
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hba->mcq_opr[OPR_SQD].offset = REG_UFS_MTK_SQD;
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hba->mcq_opr[OPR_SQIS].offset = REG_UFS_MTK_SQIS;
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hba->mcq_opr[OPR_CQD].offset = REG_UFS_MTK_CQD;
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hba->mcq_opr[OPR_CQIS].offset = REG_UFS_MTK_CQIS;
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for (i = 0; i < OPR_MAX; i++) {
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opr = &hba->mcq_opr[i];
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opr->stride = REG_UFS_MCQ_STRIDE;
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opr->base = hba->mmio_base + opr->offset;
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}
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return 0;
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}
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static int ufs_mtk_mcq_config_resource(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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/* fail mcq initialization if interrupt is not filled properly */
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if (!host->mcq_nr_intr) {
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dev_info(hba->dev, "IRQs not ready. MCQ disabled.");
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return -EINVAL;
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}
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hba->mcq_base = hba->mmio_base + MCQ_QUEUE_OFFSET(hba->mcq_capabilities);
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return 0;
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}
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static irqreturn_t ufs_mtk_mcq_intr(int irq, void *__intr_info)
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{
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struct ufs_mtk_mcq_intr_info *mcq_intr_info = __intr_info;
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struct ufs_hba *hba = mcq_intr_info->hba;
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struct ufs_hw_queue *hwq;
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u32 events;
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int qid = mcq_intr_info->qid;
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hwq = &hba->uhq[qid];
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events = ufshcd_mcq_read_cqis(hba, qid);
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if (events)
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ufshcd_mcq_write_cqis(hba, events, qid);
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if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS)
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ufshcd_mcq_poll_cqe_lock(hba, hwq);
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return IRQ_HANDLED;
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}
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static int ufs_mtk_config_mcq_irq(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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u32 irq, i;
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int ret;
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for (i = 0; i < host->mcq_nr_intr; i++) {
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irq = host->mcq_intr_info[i].irq;
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if (irq == MTK_MCQ_INVALID_IRQ) {
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dev_err(hba->dev, "invalid irq. %d\n", i);
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return -ENOPARAM;
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}
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host->mcq_intr_info[i].qid = i;
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ret = devm_request_irq(hba->dev, irq, ufs_mtk_mcq_intr, 0, UFSHCD,
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&host->mcq_intr_info[i]);
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dev_dbg(hba->dev, "request irq %d intr %s\n", irq, ret ? "failed" : "");
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if (ret) {
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dev_err(hba->dev, "Cannot request irq %d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static int ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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int ret = 0;
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if (!host->mcq_set_intr) {
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/* Disable irq option register */
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ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, 0, REG_UFS_MMIO_OPT_CTRL_0);
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if (irq) {
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ret = ufs_mtk_config_mcq_irq(hba);
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if (ret)
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return ret;
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}
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host->mcq_set_intr = true;
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}
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ufshcd_rmwl(hba, MCQ_AH8, MCQ_AH8, REG_UFS_MMIO_OPT_CTRL_0);
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ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, MCQ_MULTI_INTR_EN, REG_UFS_MMIO_OPT_CTRL_0);
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return 0;
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}
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static int ufs_mtk_config_esi(struct ufs_hba *hba)
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{
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return ufs_mtk_config_mcq(hba, true);
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}
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/*
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* struct ufs_hba_mtk_vops - UFS MTK specific variant operations
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*
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@ -1520,6 +1685,11 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
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.event_notify = ufs_mtk_event_notify,
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.config_scaling_param = ufs_mtk_config_scaling_param,
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.clk_scale_notify = ufs_mtk_clk_scale_notify,
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/* mcq vops */
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.get_hba_mac = ufs_mtk_get_hba_mac,
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.op_runtime_config = ufs_mtk_op_runtime_config,
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.mcq_config_resource = ufs_mtk_mcq_config_resource,
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.config_esi = ufs_mtk_config_esi,
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};
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/**
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@ -1566,7 +1736,7 @@ skip_reset:
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out:
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if (err)
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dev_info(dev, "probe failed %d\n", err);
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dev_err(dev, "probe failed %d\n", err);
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of_node_put(reset_node);
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return err;
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@ -10,11 +10,27 @@
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#include <linux/pm_qos.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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/*
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* MCQ define and struct
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*/
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#define UFSHCD_MAX_Q_NR 8
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#define MTK_MCQ_INVALID_IRQ 0xFFFF
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/* REG_UFS_MMIO_OPT_CTRL_0 160h */
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#define EHS_EN BIT(0)
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#define PFM_IMPV BIT(1)
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#define MCQ_MULTI_INTR_EN BIT(2)
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#define MCQ_CMB_INTR_EN BIT(3)
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#define MCQ_AH8 BIT(4)
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#define MCQ_INTR_EN_MSK (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN)
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/*
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* Vendor specific UFSHCI Registers
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*/
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#define REG_UFS_XOUFS_CTRL 0x140
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#define REG_UFS_REFCLK_CTRL 0x144
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#define REG_UFS_MMIO_OPT_CTRL_0 0x160
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#define REG_UFS_EXTREG 0x2100
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#define REG_UFS_MPHYCTRL 0x2200
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#define REG_UFS_MTK_IP_VER 0x2240
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@ -26,6 +42,13 @@
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#define REG_UFS_DEBUG_SEL_B2 0x22D8
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#define REG_UFS_DEBUG_SEL_B3 0x22DC
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#define REG_UFS_MTK_SQD 0x2800
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#define REG_UFS_MTK_SQIS 0x2814
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#define REG_UFS_MTK_CQD 0x281C
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#define REG_UFS_MTK_CQIS 0x2824
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#define REG_UFS_MCQ_STRIDE 0x30
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/*
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* Ref-clk control
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*
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@ -136,6 +159,12 @@ struct ufs_mtk_hw_ver {
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u8 major;
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};
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struct ufs_mtk_mcq_intr_info {
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struct ufs_hba *hba;
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u32 irq;
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u8 qid;
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};
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struct ufs_mtk_host {
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struct phy *mphy;
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struct pm_qos_request pm_qos_req;
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@ -155,6 +184,10 @@ struct ufs_mtk_host {
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u16 ref_clk_ungating_wait_us;
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u16 ref_clk_gating_wait_us;
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u32 ip_ver;
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bool mcq_set_intr;
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int mcq_nr_intr;
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struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
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};
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/*
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