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dmaengine: Loongson1: Add Loongson-1 APB DMA driver
Add APB DMA driver for Loongson-1 SoCs. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Link: https://lore.kernel.org/r/20240809-loongson1-dma-v12-2-d9469a4a6b85@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Keguang Zhang
Vinod Koul
parent
7ea270bb93
commit
e06c432312
@ -369,6 +369,15 @@ config K3_DMA
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Support the DMA engine for Hisilicon K3 platform
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devices.
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config LOONGSON1_APB_DMA
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tristate "Loongson1 APB DMA support"
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depends on MACH_LOONGSON32 || COMPILE_TEST
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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This selects support for the APB DMA controller in Loongson1 SoCs,
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which is required by Loongson1 NAND and audio support.
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config LPC18XX_DMAMUX
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bool "NXP LPC18xx/43xx DMA MUX for PL080"
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depends on ARCH_LPC18XX || COMPILE_TEST
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@ -49,6 +49,7 @@ obj-$(CONFIG_INTEL_IDMA64) += idma64.o
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obj-$(CONFIG_INTEL_IOATDMA) += ioat/
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obj-y += idxd/
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obj-$(CONFIG_K3_DMA) += k3dma.o
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obj-$(CONFIG_LOONGSON1_APB_DMA) += loongson1-apb-dma.o
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obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o
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obj-$(CONFIG_LS2X_APB_DMA) += ls2x-apb-dma.o
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obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o
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660
drivers/dma/loongson1-apb-dma.c
Normal file
660
drivers/dma/loongson1-apb-dma.c
Normal file
@ -0,0 +1,660 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for Loongson-1 APB DMA Controller
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*
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* Copyright (C) 2015-2024 Keguang Zhang <keguang.zhang@gmail.com>
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*/
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#include <linux/dmapool.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "dmaengine.h"
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#include "virt-dma.h"
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/* Loongson-1 DMA Control Register */
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#define LS1X_DMA_CTRL 0x0
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/* DMA Control Register Bits */
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#define LS1X_DMA_STOP BIT(4)
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#define LS1X_DMA_START BIT(3)
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#define LS1X_DMA_ASK_VALID BIT(2)
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/* DMA Next Field Bits */
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#define LS1X_DMA_NEXT_VALID BIT(0)
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/* DMA Command Field Bits */
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#define LS1X_DMA_RAM2DEV BIT(12)
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#define LS1X_DMA_INT BIT(1)
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#define LS1X_DMA_INT_MASK BIT(0)
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#define LS1X_DMA_LLI_ALIGNMENT 64
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#define LS1X_DMA_LLI_ADDR_MASK GENMASK(31, __ffs(LS1X_DMA_LLI_ALIGNMENT))
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#define LS1X_DMA_MAX_CHANNELS 3
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enum ls1x_dmadesc_offsets {
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LS1X_DMADESC_NEXT = 0,
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LS1X_DMADESC_SADDR,
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LS1X_DMADESC_DADDR,
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LS1X_DMADESC_LENGTH,
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LS1X_DMADESC_STRIDE,
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LS1X_DMADESC_CYCLES,
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LS1X_DMADESC_CMD,
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LS1X_DMADESC_SIZE
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};
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struct ls1x_dma_lli {
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unsigned int hw[LS1X_DMADESC_SIZE];
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dma_addr_t phys;
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struct list_head node;
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} __aligned(LS1X_DMA_LLI_ALIGNMENT);
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struct ls1x_dma_desc {
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struct virt_dma_desc vd;
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struct list_head lli_list;
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};
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struct ls1x_dma_chan {
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struct virt_dma_chan vc;
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struct dma_pool *lli_pool;
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phys_addr_t src_addr;
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phys_addr_t dst_addr;
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enum dma_slave_buswidth src_addr_width;
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enum dma_slave_buswidth dst_addr_width;
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unsigned int bus_width;
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void __iomem *reg_base;
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int irq;
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bool is_cyclic;
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struct ls1x_dma_lli *curr_lli;
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};
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struct ls1x_dma {
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struct dma_device ddev;
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unsigned int nr_chans;
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struct ls1x_dma_chan chan[];
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};
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static irqreturn_t ls1x_dma_irq_handler(int irq, void *data);
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#define to_ls1x_dma_chan(dchan) \
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container_of(dchan, struct ls1x_dma_chan, vc.chan)
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#define to_ls1x_dma_desc(d) \
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container_of(d, struct ls1x_dma_desc, vd)
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static inline struct device *chan2dev(struct dma_chan *chan)
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{
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return &chan->dev->device;
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}
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static inline int ls1x_dma_query(struct ls1x_dma_chan *chan,
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dma_addr_t *lli_phys)
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{
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struct dma_chan *dchan = &chan->vc.chan;
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int val, ret;
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val = *lli_phys & LS1X_DMA_LLI_ADDR_MASK;
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val |= LS1X_DMA_ASK_VALID;
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val |= dchan->chan_id;
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writel(val, chan->reg_base + LS1X_DMA_CTRL);
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ret = readl_poll_timeout_atomic(chan->reg_base + LS1X_DMA_CTRL, val,
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!(val & LS1X_DMA_ASK_VALID), 0, 3000);
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if (ret)
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dev_err(chan2dev(dchan), "failed to query DMA\n");
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return ret;
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}
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static inline int ls1x_dma_start(struct ls1x_dma_chan *chan,
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dma_addr_t *lli_phys)
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{
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struct dma_chan *dchan = &chan->vc.chan;
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struct device *dev = chan2dev(dchan);
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int val, ret;
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val = *lli_phys & LS1X_DMA_LLI_ADDR_MASK;
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val |= LS1X_DMA_START;
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val |= dchan->chan_id;
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writel(val, chan->reg_base + LS1X_DMA_CTRL);
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ret = readl_poll_timeout(chan->reg_base + LS1X_DMA_CTRL, val,
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!(val & LS1X_DMA_START), 0, 1000);
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if (!ret)
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dev_dbg(dev, "start DMA with lli_phys=%pad\n", lli_phys);
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else
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dev_err(dev, "failed to start DMA\n");
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return ret;
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}
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static inline void ls1x_dma_stop(struct ls1x_dma_chan *chan)
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{
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int val = readl(chan->reg_base + LS1X_DMA_CTRL);
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writel(val | LS1X_DMA_STOP, chan->reg_base + LS1X_DMA_CTRL);
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}
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static void ls1x_dma_free_chan_resources(struct dma_chan *dchan)
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{
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struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
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struct device *dev = chan2dev(dchan);
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dma_free_coherent(dev, sizeof(struct ls1x_dma_lli),
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chan->curr_lli, chan->curr_lli->phys);
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dma_pool_destroy(chan->lli_pool);
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chan->lli_pool = NULL;
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devm_free_irq(dev, chan->irq, chan);
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vchan_free_chan_resources(&chan->vc);
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}
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static int ls1x_dma_alloc_chan_resources(struct dma_chan *dchan)
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{
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struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
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struct device *dev = chan2dev(dchan);
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dma_addr_t phys;
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int ret;
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ret = devm_request_irq(dev, chan->irq, ls1x_dma_irq_handler,
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IRQF_SHARED, dma_chan_name(dchan), chan);
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if (ret) {
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dev_err(dev, "failed to request IRQ %d\n", chan->irq);
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return ret;
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}
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chan->lli_pool = dma_pool_create(dma_chan_name(dchan), dev,
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sizeof(struct ls1x_dma_lli),
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__alignof__(struct ls1x_dma_lli), 0);
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if (!chan->lli_pool)
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return -ENOMEM;
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/* allocate memory for querying the current lli */
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dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
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chan->curr_lli = dma_alloc_coherent(dev, sizeof(struct ls1x_dma_lli),
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&phys, GFP_KERNEL);
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if (!chan->curr_lli) {
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dma_pool_destroy(chan->lli_pool);
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return -ENOMEM;
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}
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chan->curr_lli->phys = phys;
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return 0;
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}
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static void ls1x_dma_free_desc(struct virt_dma_desc *vd)
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{
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struct ls1x_dma_desc *desc = to_ls1x_dma_desc(vd);
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struct ls1x_dma_chan *chan = to_ls1x_dma_chan(vd->tx.chan);
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struct ls1x_dma_lli *lli, *_lli;
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list_for_each_entry_safe(lli, _lli, &desc->lli_list, node) {
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list_del(&lli->node);
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dma_pool_free(chan->lli_pool, lli, lli->phys);
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}
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kfree(desc);
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}
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static struct ls1x_dma_desc *ls1x_dma_alloc_desc(void)
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{
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struct ls1x_dma_desc *desc;
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desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
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if (!desc)
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return NULL;
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INIT_LIST_HEAD(&desc->lli_list);
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return desc;
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}
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static int ls1x_dma_prep_lli(struct dma_chan *dchan, struct ls1x_dma_desc *desc,
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struct scatterlist *sgl, unsigned int sg_len,
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enum dma_transfer_direction dir, bool is_cyclic)
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{
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struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
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struct ls1x_dma_lli *lli, *prev = NULL, *first = NULL;
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struct device *dev = chan2dev(dchan);
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struct list_head *pos = NULL;
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struct scatterlist *sg;
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unsigned int dev_addr, cmd, i;
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switch (dir) {
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case DMA_MEM_TO_DEV:
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dev_addr = chan->dst_addr;
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chan->bus_width = chan->dst_addr_width;
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cmd = LS1X_DMA_RAM2DEV | LS1X_DMA_INT;
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break;
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case DMA_DEV_TO_MEM:
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dev_addr = chan->src_addr;
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chan->bus_width = chan->src_addr_width;
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cmd = LS1X_DMA_INT;
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break;
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default:
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dev_err(dev, "unsupported DMA direction: %s\n",
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dmaengine_get_direction_text(dir));
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return -EINVAL;
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}
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for_each_sg(sgl, sg, sg_len, i) {
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dma_addr_t buf_addr = sg_dma_address(sg);
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size_t buf_len = sg_dma_len(sg);
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dma_addr_t phys;
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if (!is_dma_copy_aligned(dchan->device, buf_addr, 0, buf_len)) {
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dev_err(dev, "buffer is not aligned\n");
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return -EINVAL;
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}
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/* allocate HW descriptors */
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lli = dma_pool_zalloc(chan->lli_pool, GFP_NOWAIT, &phys);
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if (!lli) {
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dev_err(dev, "failed to alloc lli %u\n", i);
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return -ENOMEM;
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}
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/* setup HW descriptors */
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lli->phys = phys;
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lli->hw[LS1X_DMADESC_SADDR] = buf_addr;
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lli->hw[LS1X_DMADESC_DADDR] = dev_addr;
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lli->hw[LS1X_DMADESC_LENGTH] = buf_len / chan->bus_width;
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lli->hw[LS1X_DMADESC_STRIDE] = 0;
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lli->hw[LS1X_DMADESC_CYCLES] = 1;
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lli->hw[LS1X_DMADESC_CMD] = cmd;
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if (prev)
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prev->hw[LS1X_DMADESC_NEXT] =
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lli->phys | LS1X_DMA_NEXT_VALID;
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prev = lli;
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if (!first)
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first = lli;
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list_add_tail(&lli->node, &desc->lli_list);
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}
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if (is_cyclic) {
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lli->hw[LS1X_DMADESC_NEXT] = first->phys | LS1X_DMA_NEXT_VALID;
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chan->is_cyclic = is_cyclic;
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}
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list_for_each(pos, &desc->lli_list) {
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lli = list_entry(pos, struct ls1x_dma_lli, node);
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print_hex_dump_debug("LLI: ", DUMP_PREFIX_OFFSET, 16, 4,
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lli, sizeof(*lli), false);
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}
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return 0;
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}
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static struct dma_async_tx_descriptor *
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ls1x_dma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction dir,
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unsigned long flags, void *context)
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{
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struct ls1x_dma_desc *desc;
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dev_dbg(chan2dev(dchan), "sg_len=%u flags=0x%lx dir=%s\n",
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sg_len, flags, dmaengine_get_direction_text(dir));
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desc = ls1x_dma_alloc_desc();
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if (!desc)
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return NULL;
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if (ls1x_dma_prep_lli(dchan, desc, sgl, sg_len, dir, false)) {
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ls1x_dma_free_desc(&desc->vd);
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return NULL;
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}
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return vchan_tx_prep(to_virt_chan(dchan), &desc->vd, flags);
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}
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static struct dma_async_tx_descriptor *
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ls1x_dma_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
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size_t buf_len, size_t period_len,
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enum dma_transfer_direction dir, unsigned long flags)
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{
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struct ls1x_dma_desc *desc;
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struct scatterlist *sgl;
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unsigned int sg_len;
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unsigned int i;
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int ret;
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dev_dbg(chan2dev(dchan),
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"buf_len=%zu period_len=%zu flags=0x%lx dir=%s\n",
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buf_len, period_len, flags, dmaengine_get_direction_text(dir));
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desc = ls1x_dma_alloc_desc();
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if (!desc)
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return NULL;
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/* allocate the scatterlist */
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sg_len = buf_len / period_len;
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sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_NOWAIT);
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if (!sgl)
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return NULL;
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sg_init_table(sgl, sg_len);
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for (i = 0; i < sg_len; ++i) {
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sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(buf_addr)),
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period_len, offset_in_page(buf_addr));
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sg_dma_address(&sgl[i]) = buf_addr;
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sg_dma_len(&sgl[i]) = period_len;
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buf_addr += period_len;
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}
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ret = ls1x_dma_prep_lli(dchan, desc, sgl, sg_len, dir, true);
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kfree(sgl);
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if (ret) {
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ls1x_dma_free_desc(&desc->vd);
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return NULL;
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}
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return vchan_tx_prep(to_virt_chan(dchan), &desc->vd, flags);
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}
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static int ls1x_dma_slave_config(struct dma_chan *dchan,
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struct dma_slave_config *config)
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{
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struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
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chan->src_addr = config->src_addr;
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chan->src_addr_width = config->src_addr_width;
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chan->dst_addr = config->dst_addr;
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chan->dst_addr_width = config->dst_addr_width;
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return 0;
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}
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static int ls1x_dma_pause(struct dma_chan *dchan)
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{
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struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
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int ret;
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guard(spinlock_irqsave)(&chan->vc.lock);
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/* save the current lli */
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ret = ls1x_dma_query(chan, &chan->curr_lli->phys);
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if (!ret)
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ls1x_dma_stop(chan);
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return ret;
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}
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static int ls1x_dma_resume(struct dma_chan *dchan)
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{
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struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
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guard(spinlock_irqsave)(&chan->vc.lock);
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return ls1x_dma_start(chan, &chan->curr_lli->phys);
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}
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static int ls1x_dma_terminate_all(struct dma_chan *dchan)
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{
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struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
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struct virt_dma_desc *vd;
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LIST_HEAD(head);
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ls1x_dma_stop(chan);
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scoped_guard(spinlock_irqsave, &chan->vc.lock) {
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vd = vchan_next_desc(&chan->vc);
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if (vd)
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vchan_terminate_vdesc(vd);
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|
||||
vchan_get_all_descriptors(&chan->vc, &head);
|
||||
}
|
||||
|
||||
vchan_dma_desc_free_list(&chan->vc, &head);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ls1x_dma_synchronize(struct dma_chan *dchan)
|
||||
{
|
||||
vchan_synchronize(to_virt_chan(dchan));
|
||||
}
|
||||
|
||||
static enum dma_status ls1x_dma_tx_status(struct dma_chan *dchan,
|
||||
dma_cookie_t cookie,
|
||||
struct dma_tx_state *state)
|
||||
{
|
||||
struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
|
||||
struct virt_dma_desc *vd;
|
||||
enum dma_status status;
|
||||
size_t bytes = 0;
|
||||
|
||||
status = dma_cookie_status(dchan, cookie, state);
|
||||
if (status == DMA_COMPLETE)
|
||||
return status;
|
||||
|
||||
scoped_guard(spinlock_irqsave, &chan->vc.lock) {
|
||||
vd = vchan_find_desc(&chan->vc, cookie);
|
||||
if (vd) {
|
||||
struct ls1x_dma_desc *desc = to_ls1x_dma_desc(vd);
|
||||
struct ls1x_dma_lli *lli;
|
||||
dma_addr_t next_phys;
|
||||
|
||||
/* get the current lli */
|
||||
if (ls1x_dma_query(chan, &chan->curr_lli->phys))
|
||||
return status;
|
||||
|
||||
/* locate the current lli */
|
||||
next_phys = chan->curr_lli->hw[LS1X_DMADESC_NEXT];
|
||||
list_for_each_entry(lli, &desc->lli_list, node)
|
||||
if (lli->hw[LS1X_DMADESC_NEXT] == next_phys)
|
||||
break;
|
||||
|
||||
dev_dbg(chan2dev(dchan), "current lli_phys=%pad",
|
||||
&lli->phys);
|
||||
|
||||
/* count the residues */
|
||||
list_for_each_entry_from(lli, &desc->lli_list, node)
|
||||
bytes += lli->hw[LS1X_DMADESC_LENGTH] *
|
||||
chan->bus_width;
|
||||
}
|
||||
}
|
||||
|
||||
dma_set_residue(state, bytes);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void ls1x_dma_issue_pending(struct dma_chan *dchan)
|
||||
{
|
||||
struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
|
||||
|
||||
guard(spinlock_irqsave)(&chan->vc.lock);
|
||||
|
||||
if (vchan_issue_pending(&chan->vc)) {
|
||||
struct virt_dma_desc *vd = vchan_next_desc(&chan->vc);
|
||||
|
||||
if (vd) {
|
||||
struct ls1x_dma_desc *desc = to_ls1x_dma_desc(vd);
|
||||
struct ls1x_dma_lli *lli;
|
||||
|
||||
lli = list_first_entry(&desc->lli_list,
|
||||
struct ls1x_dma_lli, node);
|
||||
ls1x_dma_start(chan, &lli->phys);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t ls1x_dma_irq_handler(int irq, void *data)
|
||||
{
|
||||
struct ls1x_dma_chan *chan = data;
|
||||
struct dma_chan *dchan = &chan->vc.chan;
|
||||
struct device *dev = chan2dev(dchan);
|
||||
struct virt_dma_desc *vd;
|
||||
|
||||
scoped_guard(spinlock, &chan->vc.lock) {
|
||||
vd = vchan_next_desc(&chan->vc);
|
||||
if (!vd) {
|
||||
dev_warn(dev,
|
||||
"IRQ %d with no active desc on channel %d\n",
|
||||
irq, dchan->chan_id);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
if (chan->is_cyclic) {
|
||||
vchan_cyclic_callback(vd);
|
||||
} else {
|
||||
list_del(&vd->node);
|
||||
vchan_cookie_complete(vd);
|
||||
}
|
||||
}
|
||||
|
||||
dev_dbg(dev, "DMA IRQ %d on channel %d\n", irq, dchan->chan_id);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int ls1x_dma_chan_probe(struct platform_device *pdev,
|
||||
struct ls1x_dma *dma)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
int id;
|
||||
|
||||
reg_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(reg_base))
|
||||
return PTR_ERR(reg_base);
|
||||
|
||||
for (id = 0; id < dma->nr_chans; id++) {
|
||||
struct ls1x_dma_chan *chan = &dma->chan[id];
|
||||
char pdev_irqname[4];
|
||||
|
||||
sprintf(pdev_irqname, "ch%d", id);
|
||||
chan->irq = platform_get_irq_byname(pdev, pdev_irqname);
|
||||
if (chan->irq < 0)
|
||||
return dev_err_probe(&pdev->dev, chan->irq,
|
||||
"failed to get IRQ for ch%d\n",
|
||||
id);
|
||||
|
||||
chan->reg_base = reg_base;
|
||||
chan->vc.desc_free = ls1x_dma_free_desc;
|
||||
vchan_init(&chan->vc, &dma->ddev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ls1x_dma_chan_remove(struct ls1x_dma *dma)
|
||||
{
|
||||
int id;
|
||||
|
||||
for (id = 0; id < dma->nr_chans; id++) {
|
||||
struct ls1x_dma_chan *chan = &dma->chan[id];
|
||||
|
||||
if (chan->vc.chan.device == &dma->ddev) {
|
||||
list_del(&chan->vc.chan.device_node);
|
||||
tasklet_kill(&chan->vc.task);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int ls1x_dma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct dma_device *ddev;
|
||||
struct ls1x_dma *dma;
|
||||
int ret;
|
||||
|
||||
ret = platform_irq_count(pdev);
|
||||
if (ret <= 0 || ret > LS1X_DMA_MAX_CHANNELS)
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"Invalid number of IRQ channels: %d\n",
|
||||
ret);
|
||||
|
||||
dma = devm_kzalloc(dev, struct_size(dma, chan, ret), GFP_KERNEL);
|
||||
if (!dma)
|
||||
return -ENOMEM;
|
||||
dma->nr_chans = ret;
|
||||
|
||||
/* initialize DMA device */
|
||||
ddev = &dma->ddev;
|
||||
ddev->dev = dev;
|
||||
ddev->copy_align = DMAENGINE_ALIGN_4_BYTES;
|
||||
ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
|
||||
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
|
||||
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
|
||||
ddev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
|
||||
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
|
||||
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
|
||||
ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
||||
ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
|
||||
ddev->device_alloc_chan_resources = ls1x_dma_alloc_chan_resources;
|
||||
ddev->device_free_chan_resources = ls1x_dma_free_chan_resources;
|
||||
ddev->device_prep_slave_sg = ls1x_dma_prep_slave_sg;
|
||||
ddev->device_prep_dma_cyclic = ls1x_dma_prep_dma_cyclic;
|
||||
ddev->device_config = ls1x_dma_slave_config;
|
||||
ddev->device_pause = ls1x_dma_pause;
|
||||
ddev->device_resume = ls1x_dma_resume;
|
||||
ddev->device_terminate_all = ls1x_dma_terminate_all;
|
||||
ddev->device_synchronize = ls1x_dma_synchronize;
|
||||
ddev->device_tx_status = ls1x_dma_tx_status;
|
||||
ddev->device_issue_pending = ls1x_dma_issue_pending;
|
||||
dma_cap_set(DMA_SLAVE, ddev->cap_mask);
|
||||
INIT_LIST_HEAD(&ddev->channels);
|
||||
|
||||
/* initialize DMA channels */
|
||||
ret = ls1x_dma_chan_probe(pdev, dma);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = dmaenginem_async_device_register(ddev);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register DMA device\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = of_dma_controller_register(dev->of_node, of_dma_xlate_by_chan_id,
|
||||
ddev);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register DMA controller\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, dma);
|
||||
dev_info(dev, "Loongson1 DMA driver registered\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
ls1x_dma_chan_remove(dma);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ls1x_dma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ls1x_dma *dma = platform_get_drvdata(pdev);
|
||||
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
ls1x_dma_chan_remove(dma);
|
||||
}
|
||||
|
||||
static const struct of_device_id ls1x_dma_match[] = {
|
||||
{ .compatible = "loongson,ls1b-apbdma" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ls1x_dma_match);
|
||||
|
||||
static struct platform_driver ls1x_dma_driver = {
|
||||
.probe = ls1x_dma_probe,
|
||||
.remove = ls1x_dma_remove,
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.of_match_table = ls1x_dma_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(ls1x_dma_driver);
|
||||
|
||||
MODULE_AUTHOR("Keguang Zhang <keguang.zhang@gmail.com>");
|
||||
MODULE_DESCRIPTION("Loongson-1 APB DMA Controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user