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powerpc/perf: Power8 PMU support
This patch adds support for the power8 PMU to perf. Work is ongoing to add generic cache events. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Michael Ellerman
Benjamin Herrenschmidt
parent
8f61aa325f
commit
e05b9b9e5c
@ -4,7 +4,8 @@ obj-$(CONFIG_PERF_EVENTS) += callchain.o
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obj-$(CONFIG_PPC_PERF_CTRS) += core-book3s.o
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obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \
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power5+-pmu.o power6-pmu.o power7-pmu.o
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power5+-pmu.o power6-pmu.o power7-pmu.o \
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power8-pmu.o
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obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
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obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
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537
arch/powerpc/perf/power8-pmu.c
Normal file
537
arch/powerpc/perf/power8-pmu.c
Normal file
@ -0,0 +1,537 @@
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/*
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* Performance counter support for POWER8 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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* Copyright 2013 Michael Ellerman, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/perf_event.h>
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#include <asm/firmware.h>
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/*
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* Some power8 event codes.
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*/
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#define PM_CYC 0x0001e
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#define PM_GCT_NOSLOT_CYC 0x100f8
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#define PM_CMPLU_STALL 0x4000a
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#define PM_INST_CMPL 0x00002
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#define PM_BRU_FIN 0x10068
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#define PM_BR_MPRED_CMPL 0x400f6
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/*
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* Raw event encoding for POWER8:
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*
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* 60 56 52 48 44 40 36 32
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ thresh_cmp ] [ thresh_ctl ]
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* |
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* thresh start/stop OR FAB match -*
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*
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* 28 24 20 16 12 8 4 0
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel ]
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* | | | | |
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* | | | | *- mark
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* | | *- L1/L2/L3 cache_sel |
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* | | |
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* | *- sampling mode for marked events *- combine
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* |
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* *- thresh_sel
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*
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* Below uses IBM bit numbering.
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*
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* MMCR1[x:y] = unit (PMCxUNIT)
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* MMCR1[x] = combine (PMCxCOMB)
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*
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* if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
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* # PM_MRK_FAB_RSP_MATCH
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* MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
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* else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
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* # PM_MRK_FAB_RSP_MATCH_CYC
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* MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
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* else
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* MMCRA[48:55] = thresh_ctl (THRESH START/END)
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*
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* if thresh_sel:
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* MMCRA[45:47] = thresh_sel
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*
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* if thresh_cmp:
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* MMCRA[22:24] = thresh_cmp[0:2]
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* MMCRA[25:31] = thresh_cmp[3:9]
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*
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* if unit == 6 or unit == 7
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* MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
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* else if unit == 8 or unit == 9:
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* if cache_sel[0] == 0: # L3 bank
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* MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
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* else if cache_sel[0] == 1:
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* MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1)
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* else if cache_sel[1]: # L1 event
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* MMCR1[16] = cache_sel[2]
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* MMCR1[17] = cache_sel[3]
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*
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* if mark:
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* MMCRA[63] = 1 (SAMPLE_ENABLE)
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* MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
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* MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
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*
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*/
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#define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */
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#define EVENT_THR_CMP_MASK 0x3ff
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#define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */
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#define EVENT_THR_CTL_MASK 0xffull
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#define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */
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#define EVENT_THR_SEL_MASK 0x7
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#define EVENT_THRESH_SHIFT 29 /* All threshold bits */
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#define EVENT_THRESH_MASK 0x1fffffull
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#define EVENT_SAMPLE_SHIFT 24 /* Sampling mode & eligibility */
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#define EVENT_SAMPLE_MASK 0x1f
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#define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */
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#define EVENT_CACHE_SEL_MASK 0xf
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#define EVENT_IS_L1 (4 << EVENT_CACHE_SEL_SHIFT)
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#define EVENT_PMC_SHIFT 16 /* PMC number (1-based) */
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#define EVENT_PMC_MASK 0xf
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#define EVENT_UNIT_SHIFT 12 /* Unit */
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#define EVENT_UNIT_MASK 0xf
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#define EVENT_COMBINE_SHIFT 11 /* Combine bit */
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#define EVENT_COMBINE_MASK 0x1
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#define EVENT_MARKED_SHIFT 8 /* Marked bit */
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#define EVENT_MARKED_MASK 0x1
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#define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
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#define EVENT_PSEL_MASK 0xff /* PMCxSEL value */
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/*
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* Layout of constraint bits:
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*
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* 60 56 52 48 44 40 36 32
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
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* |
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* thresh_sel -*
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*
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* 28 24 20 16 12 8 4 0
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1]
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* | |
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* L1 I/D qualifier -* | Count of events for each PMC.
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* | p1, p2, p3, p4, p5, p6.
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* nc - number of counters -*
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*
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* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
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* we want the low bit of each field to be added to any existing value.
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*
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* Everything else is a value field.
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*/
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#define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56)
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#define CNST_FAB_MATCH_MASK CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
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/* We just throw all the threshold bits into the constraint */
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#define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
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#define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK)
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#define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22)
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#define CNST_L1_QUAL_MASK CNST_L1_QUAL_VAL(3)
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#define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16)
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#define CNST_SAMPLE_MASK CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
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/*
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* For NC we are counting up to 4 events. This requires three bits, and we need
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* the fifth event to overflow and set the 4th bit. To achieve that we bias the
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* fields by 3 in test_adder.
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*/
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#define CNST_NC_SHIFT 12
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#define CNST_NC_VAL (1 << CNST_NC_SHIFT)
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#define CNST_NC_MASK (8 << CNST_NC_SHIFT)
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#define POWER8_TEST_ADDER (3 << CNST_NC_SHIFT)
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/*
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* For the per-PMC fields we have two bits. The low bit is added, so if two
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* events ask for the same PMC the sum will overflow, setting the high bit,
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* indicating an error. So our mask sets the high bit.
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*/
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#define CNST_PMC_SHIFT(pmc) ((pmc - 1) * 2)
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#define CNST_PMC_VAL(pmc) (1 << CNST_PMC_SHIFT(pmc))
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#define CNST_PMC_MASK(pmc) (2 << CNST_PMC_SHIFT(pmc))
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/* Our add_fields is defined as: */
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#define POWER8_ADD_FIELDS \
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CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
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CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
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/* Bits in MMCR1 for POWER8 */
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#define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1)))
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#define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1))
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#define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8)
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#define MMCR1_DC_QUAL_SHIFT 47
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#define MMCR1_IC_QUAL_SHIFT 46
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/* Bits in MMCRA for POWER8 */
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#define MMCRA_SAMP_MODE_SHIFT 1
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#define MMCRA_SAMP_ELIG_SHIFT 4
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#define MMCRA_THR_CTL_SHIFT 8
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#define MMCRA_THR_SEL_SHIFT 16
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#define MMCRA_THR_CMP_SHIFT 32
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#define MMCRA_SDAR_MODE_TLB (1ull << 42)
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static inline bool event_is_fab_match(u64 event)
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{
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/* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
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event &= 0xff0fe;
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/* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
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return (event == 0x30056 || event == 0x4f052);
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}
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static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
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{
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unsigned int unit, pmc, cache;
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unsigned long mask, value;
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mask = value = 0;
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pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
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cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
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if (pmc) {
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if (pmc > 6)
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return -1;
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mask |= CNST_PMC_MASK(pmc);
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value |= CNST_PMC_VAL(pmc);
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if (pmc >= 5 && event != 0x500fa && event != 0x600f4)
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return -1;
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}
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if (pmc <= 4) {
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/*
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* Add to number of counters in use. Note this includes events with
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* a PMC of 0 - they still need a PMC, it's just assigned later.
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* Don't count events on PMC 5 & 6, there is only one valid event
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* on each of those counters, and they are handled above.
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*/
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mask |= CNST_NC_MASK;
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value |= CNST_NC_VAL;
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}
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if (unit >= 6 && unit <= 9) {
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/*
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* L2/L3 events contain a cache selector field, which is
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* supposed to be programmed into MMCRC. However MMCRC is only
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* HV writable, and there is no API for guest kernels to modify
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* it. The solution is for the hypervisor to initialise the
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* field to zeroes, and for us to only ever allow events that
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* have a cache selector of zero.
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*/
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if (cache)
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return -1;
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} else if (event & EVENT_IS_L1) {
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mask |= CNST_L1_QUAL_MASK;
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value |= CNST_L1_QUAL_VAL(cache);
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}
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if (event & EVENT_IS_MARKED) {
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mask |= CNST_SAMPLE_MASK;
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value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
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}
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/*
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* Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
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* the threshold control bits are used for the match value.
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*/
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if (event_is_fab_match(event)) {
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mask |= CNST_FAB_MATCH_MASK;
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value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
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} else {
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/*
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* Check the mantissa upper two bits are not zero, unless the
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* exponent is also zero. See the THRESH_CMP_MANTISSA doc.
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*/
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unsigned int cmp, exp;
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cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
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exp = cmp >> 7;
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if (exp && (cmp & 0x60) == 0)
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return -1;
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mask |= CNST_THRESH_MASK;
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value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
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}
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*maskp = mask;
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*valp = value;
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return 0;
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}
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static int power8_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[])
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{
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unsigned long mmcra, mmcr1, unit, combine, psel, cache, val;
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unsigned int pmc, pmc_inuse;
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int i;
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pmc_inuse = 0;
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/* First pass to count resource use */
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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if (pmc)
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pmc_inuse |= 1 << pmc;
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}
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/* In continous sampling mode, update SDAR on TLB miss */
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mmcra = MMCRA_SDAR_MODE_TLB;
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mmcr1 = 0;
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/* Second pass: assign PMCs, set all MMCR1 fields */
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
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combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
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psel = event[i] & EVENT_PSEL_MASK;
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if (!pmc) {
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for (pmc = 1; pmc <= 4; ++pmc) {
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if (!(pmc_inuse & (1 << pmc)))
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break;
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}
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pmc_inuse |= 1 << pmc;
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}
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if (pmc <= 4) {
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mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
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mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc);
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mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
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}
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if (event[i] & EVENT_IS_L1) {
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cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
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mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
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cache >>= 1;
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mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
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}
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if (event[i] & EVENT_IS_MARKED) {
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mmcra |= MMCRA_SAMPLE_ENABLE;
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val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
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if (val) {
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mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
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mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
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}
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}
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/*
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* PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
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* the threshold bits are used for the match value.
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*/
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if (event_is_fab_match(event[i])) {
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mmcr1 |= (event[i] >> EVENT_THR_CTL_SHIFT) &
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EVENT_THR_CTL_MASK;
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} else {
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val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
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mmcra |= val << MMCRA_THR_CTL_SHIFT;
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val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
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mmcra |= val << MMCRA_THR_SEL_SHIFT;
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val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
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mmcra |= val << MMCRA_THR_CMP_SHIFT;
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}
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hwc[i] = pmc - 1;
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}
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/* Return MMCRx values */
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mmcr[0] = 0;
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/* pmc_inuse is 1-based */
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if (pmc_inuse & 2)
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mmcr[0] = MMCR0_PMC1CE;
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if (pmc_inuse & 0x7c)
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mmcr[0] |= MMCR0_PMCjCE;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcra;
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return 0;
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}
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#define MAX_ALT 2
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/* Table of alternatives, sorted by column 0 */
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ 0x10134, 0x301e2 }, /* PM_MRK_ST_CMPL */
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{ 0x10138, 0x40138 }, /* PM_BR_MRK_2PATH */
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{ 0x18082, 0x3e05e }, /* PM_L3_CO_MEPF */
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{ 0x1d14e, 0x401e8 }, /* PM_MRK_DATA_FROM_L2MISS */
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{ 0x1e054, 0x4000a }, /* PM_CMPLU_STALL */
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{ 0x20036, 0x40036 }, /* PM_BR_2PATH */
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{ 0x200f2, 0x300f2 }, /* PM_INST_DISP */
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{ 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
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{ 0x2013c, 0x3012e }, /* PM_MRK_FILT_MATCH */
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||||
{ 0x3e054, 0x400f0 }, /* PM_LD_MISS_L1 */
|
||||
{ 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
|
||||
};
|
||||
|
||||
/*
|
||||
* Scan the alternatives table for a match and return the
|
||||
* index into the alternatives table if found, else -1.
|
||||
*/
|
||||
static int find_alternative(u64 event)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
|
||||
if (event < event_alternatives[i][0])
|
||||
break;
|
||||
|
||||
for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
|
||||
if (event == event_alternatives[i][j])
|
||||
return i;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
|
||||
{
|
||||
int i, j, num_alt = 0;
|
||||
u64 alt_event;
|
||||
|
||||
alt[num_alt++] = event;
|
||||
|
||||
i = find_alternative(event);
|
||||
if (i >= 0) {
|
||||
/* Filter out the original event, it's already in alt[0] */
|
||||
for (j = 0; j < MAX_ALT; ++j) {
|
||||
alt_event = event_alternatives[i][j];
|
||||
if (alt_event && alt_event != event)
|
||||
alt[num_alt++] = alt_event;
|
||||
}
|
||||
}
|
||||
|
||||
if (flags & PPMU_ONLY_COUNT_RUN) {
|
||||
/*
|
||||
* We're only counting in RUN state, so PM_CYC is equivalent to
|
||||
* PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
|
||||
*/
|
||||
j = num_alt;
|
||||
for (i = 0; i < num_alt; ++i) {
|
||||
switch (alt[i]) {
|
||||
case 0x1e: /* PM_CYC */
|
||||
alt[j++] = 0x600f4; /* PM_RUN_CYC */
|
||||
break;
|
||||
case 0x600f4: /* PM_RUN_CYC */
|
||||
alt[j++] = 0x1e;
|
||||
break;
|
||||
case 0x2: /* PM_PPC_CMPL */
|
||||
alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
|
||||
break;
|
||||
case 0x500fa: /* PM_RUN_INST_CMPL */
|
||||
alt[j++] = 0x2; /* PM_PPC_CMPL */
|
||||
break;
|
||||
}
|
||||
}
|
||||
num_alt = j;
|
||||
}
|
||||
|
||||
return num_alt;
|
||||
}
|
||||
|
||||
static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[])
|
||||
{
|
||||
if (pmc <= 3)
|
||||
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
|
||||
}
|
||||
|
||||
PMU_FORMAT_ATTR(event, "config:0-49");
|
||||
PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
|
||||
PMU_FORMAT_ATTR(mark, "config:8");
|
||||
PMU_FORMAT_ATTR(combine, "config:11");
|
||||
PMU_FORMAT_ATTR(unit, "config:12-15");
|
||||
PMU_FORMAT_ATTR(pmc, "config:16-19");
|
||||
PMU_FORMAT_ATTR(cache_sel, "config:20-23");
|
||||
PMU_FORMAT_ATTR(sample_mode, "config:24-28");
|
||||
PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
|
||||
PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
|
||||
PMU_FORMAT_ATTR(thresh_start, "config:36-39");
|
||||
PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
|
||||
|
||||
static struct attribute *power8_pmu_format_attr[] = {
|
||||
&format_attr_event.attr,
|
||||
&format_attr_pmcxsel.attr,
|
||||
&format_attr_mark.attr,
|
||||
&format_attr_combine.attr,
|
||||
&format_attr_unit.attr,
|
||||
&format_attr_pmc.attr,
|
||||
&format_attr_cache_sel.attr,
|
||||
&format_attr_sample_mode.attr,
|
||||
&format_attr_thresh_sel.attr,
|
||||
&format_attr_thresh_stop.attr,
|
||||
&format_attr_thresh_start.attr,
|
||||
&format_attr_thresh_cmp.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
struct attribute_group power8_pmu_format_group = {
|
||||
.name = "format",
|
||||
.attrs = power8_pmu_format_attr,
|
||||
};
|
||||
|
||||
static const struct attribute_group *power8_pmu_attr_groups[] = {
|
||||
&power8_pmu_format_group,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static int power8_generic_events[] = {
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
|
||||
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
|
||||
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
|
||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
|
||||
};
|
||||
|
||||
static struct power_pmu power8_pmu = {
|
||||
.name = "POWER8",
|
||||
.n_counter = 6,
|
||||
.max_alternatives = MAX_ALT + 1,
|
||||
.add_fields = POWER8_ADD_FIELDS,
|
||||
.test_adder = POWER8_TEST_ADDER,
|
||||
.compute_mmcr = power8_compute_mmcr,
|
||||
.get_constraint = power8_get_constraint,
|
||||
.get_alternatives = power8_get_alternatives,
|
||||
.disable_pmc = power8_disable_pmc,
|
||||
.flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER,
|
||||
.n_generic = ARRAY_SIZE(power8_generic_events),
|
||||
.generic_events = power8_generic_events,
|
||||
.attr_groups = power8_pmu_attr_groups,
|
||||
};
|
||||
|
||||
static int __init init_power8_pmu(void)
|
||||
{
|
||||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||||
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
|
||||
return -ENODEV;
|
||||
|
||||
return register_power_pmu(&power8_pmu);
|
||||
}
|
||||
early_initcall(init_power8_pmu);
|
||||
Loading…
Reference in New Issue
Block a user