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drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY
The current settings for 28nm PHY data lane CFG4 registers do not work with certain panels. This change is to modify them to hw recommended values. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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@ -99,16 +99,14 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97);
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}
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}
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(0), 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(1), 0x5);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(2), 0xa);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(3), 0xf);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb);
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dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb);
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