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drm/radeon: adjust default radeon_vm_block_size v2
v2: rebase on vm_size scale change. Adjust vm_size default to 8, Better handle the default and smaller values. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1123,7 +1123,19 @@ static void radeon_check_arguments(struct radeon_device *rdev)
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/* defines number of bits in page table versus page directory,
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* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
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* page table and the remaining bits are in the page directory */
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if (radeon_vm_block_size < 9) {
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if (radeon_vm_block_size == -1) {
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/* Total bits covered by PD + PTs */
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unsigned bits = ilog2(radeon_vm_size) + 17;
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/* Make sure the PD is 4K in size up to 8GB address space.
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Above that split equal between PD and PTs */
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if (radeon_vm_size <= 8)
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radeon_vm_block_size = bits - 9;
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else
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radeon_vm_block_size = (bits + 3) / 2;
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} else if (radeon_vm_block_size < 9) {
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dev_warn(rdev->dev, "VM page table size (%d) too small\n",
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radeon_vm_block_size);
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radeon_vm_block_size = 9;
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@ -175,8 +175,8 @@ int radeon_dpm = -1;
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int radeon_aspm = -1;
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int radeon_runtime_pm = -1;
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int radeon_hard_reset = 0;
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int radeon_vm_size = 4;
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int radeon_vm_block_size = 9;
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int radeon_vm_size = 8;
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int radeon_vm_block_size = -1;
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int radeon_deep_color = 0;
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MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
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@ -248,7 +248,7 @@ module_param_named(hard_reset, radeon_hard_reset, int, 0444);
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MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
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module_param_named(vm_size, radeon_vm_size, int, 0444);
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MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
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MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
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module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
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MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
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