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SoC related changes for omaps for v4.8 merge window:
- A series of DSS platform_data fixes to prepare for DSS driver changes - Add tblck clck aliases for PWM - A series of trivial spelling corrections - Remove bogus eQEP, ePWM and eCAP hwmod entries - A series of McBSP sidetone fixes - Remove QSPI and DSS addresses from hwmod, these come from dts - Fix RSTST register offset for pruss - Make ti81xx_rtc_hwmod static - Remove wrongly defined RSTST offset for PER Domain, note that the subject for this one wrongly has "dts" in the subject - Add support for omap5 and dra7 workaround for 801819 - A series of patches to make kexec work for SMP omaps -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXdMXwAAoJEBvUPslcq6VzL9oQAKfitWelEieWYINsm475xHUL DDckxrFtbVzrkI7rsY1wCi8v3i1DKEKBps47pnapy+AoD+js1C+vTKaQA2IXouFi CWlwgCuwJpLc4VoYGrbszXSJQeJowFHIH/zVk3CJrqBIwYKqnjH6sGCHRN23KNdN U2SPA7qV8XwwCrFR4e2+KWe5ulb7QsxvkCKqLyDrAwyu0wUQml1/4UjX5NYOkr1Y G5CyvGy7WBZ/t5MOFMPAR7rhxKQazUdNlgC7rGfVr+JUuYWtsyET6FBZ1kUBVFpa xc+usR78C+7gaQps8bbuIr2ymcOYamVlpjVwsvpTCWyFcnseK0hXsrf8KihRHfYh 5p1yyDlqGg5qS6B16cyNgUqi/jVNa7NuRJWavgS+oWIm1j2WkUe9gdVyqP7WQGUZ UGF4OAXoo7aykvSsYEug/5U1d4T5aShESyoukTGsLbtRGhyiSxP3OqsoHzBwyfCM bA6OZzVxR/MRinpc/udvOsi/C7erm1iA6C+Fg4Gggk59Xt0yU+e4Scg40khQQ6X9 1ND/HTG0rQ+ygLttUXPCK0kBg1u+SU/zh0+j9EV3I6CA624JQ2Gm2Bb/6xHk3vkL dmQosa5U2wLiXY6EKS2VcjAv7+yuaLdj/MMoOBh7TXz181/SnciNzAb6kEEXRNak vA0yKATY6AftMYBMwhPn =d4B3 -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.8/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc SoC related changes for omaps for v4.8 merge window: - A series of DSS platform_data fixes to prepare for DSS driver changes - Add tblck clck aliases for PWM - A series of trivial spelling corrections - Remove bogus eQEP, ePWM and eCAP hwmod entries - A series of McBSP sidetone fixes - Remove QSPI and DSS addresses from hwmod, these come from dts - Fix RSTST register offset for pruss - Make ti81xx_rtc_hwmod static - Remove wrongly defined RSTST offset for PER Domain, note that the subject for this one wrongly has "dts" in the subject - Add support for omap5 and dra7 workaround for 801819 - A series of patches to make kexec work for SMP omaps * tag 'omap-for-v4.8/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (30 commits) ARM: OMAP2+: Fix build if CONFIG_SMP is not set ARM: OMAP4+: Allow kexec on SMP variants ARM: OMAP4+: Reset CPU1 properly for kexec ARM: OMAP4+: Prevent CPU1 related hang with kexec ARM: OMAP4+: Initialize SAR RAM base early for proper CPU1 reset for kexec ARM: dts: am43xx: Remove wrongly defined RSTST offset for PER Domain ARM: OMAP: make ti81xx_rtc_hwmod static ARM: AM43XX: hwmod: Fix RSTST register offset for pruss ARM: DRA7: hwmod: remove DSS addresses from hwmod ARM: DRA7: hwmod: Remove QSPI address space entry from hwmod ARM: OMAP2+: McBSP: Remove the old iclk allow/deny idle code ASoC: omap-mcbsp: sidetone: Use the new callback for iclk handling ASoC: omap-mcbsp: Rename omap_mcbsp_sysfs_remove() to omap_mcbsp_cleanup() ARM: OMAP3: pdata-quirks: Add support for McBSP2/3 sidetone handling ARM: OMAP3: McBSP: New callback for McBSP2/3 ICLK idle configuration ARM: OMAP3: hwmod data: Fix McBSP2/3 sidetone data ARM: AM335x/AM437x: hwmod: Remove eQEP, ePWM and eCAP hwmod entries ARM: OMAP2+: Fix typo in sdrc.h ARM: OMAP2+: Fix typo in omap_device.c ARM: OMAP2+: Fix typo in omap4-common.c ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
df92d2e393
@ -136,7 +136,7 @@ void __init ams_delta_init_fiq(void)
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fiq_buffer[i] = 0;
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/*
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* FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr
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* FIQ mode r9 always points to the fiq_buffer, because the FIQ isr
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* will run in an unpredictable context. The fiq_buffer is the FIQ isr's
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* only means of communication with the IRQ level and other kernel
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* context code.
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@ -39,7 +39,7 @@ static inline unsigned long xip_omap_mpu_timer_read(int nr)
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#define xip_currtime() (~xip_omap_mpu_timer_read(0))
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/*
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* It's permitted to do approxmation for xip_elapsed_since macro
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* It's permitted to do approximation for xip_elapsed_since macro
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* (see linux/mtd/xip.h)
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*/
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@ -240,4 +240,12 @@ endmenu
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endif
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config OMAP5_ERRATA_801819
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bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
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depends on SOC_OMAP5 || SOC_DRA7XX
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help
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A livelock can occur in the L2 cache arbitration that might prevent
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a snoop from completing. Under certain conditions this can cause the
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system to deadlock.
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endmenu
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@ -8,7 +8,7 @@ ccflags-y := -I$(srctree)/$(src)/include \
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# Common support
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obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \
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common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
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omap_device.o sram.o drm.o
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omap_device.o omap-headsmp.o sram.o drm.o
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hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
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omap_hwmod_common_data.o
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@ -32,7 +32,7 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
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# SMP support ONLY available for OMAP4
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smp-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
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smp-$(CONFIG_SMP) += omap-smp.o
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smp-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
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omap-4-5-common = omap4-common.o omap-wakeupgen.o
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obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o
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@ -39,7 +39,7 @@
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#include "gpmc.h"
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#include "gpmc-smsc911x.h"
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#include <video/omapdss.h>
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#include <linux/platform_data/omapdss.h>
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#include <video/omap-panel-data.h>
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#include "board-flash.h"
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@ -47,6 +47,7 @@
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#include "hsmmc.h"
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#include "control.h"
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#include "common-board-devices.h"
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#include "display.h"
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#define LDP_SMSC911X_CS 1
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#define LDP_SMSC911X_GPIO 152
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@ -15,13 +15,14 @@
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#include <linux/spi/spi.h>
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#include <linux/mm.h>
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#include <asm/mach-types.h>
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#include <video/omapdss.h>
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#include <linux/platform_data/omapdss.h>
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#include <video/omap-panel-data.h>
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#include <linux/platform_data/spi-omap2-mcspi.h>
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#include "soc.h"
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#include "board-rx51.h"
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#include "display.h"
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#include "mux.h"
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@ -32,7 +33,6 @@
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static struct connector_atv_platform_data rx51_tv_pdata = {
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.name = "tv",
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.source = "venc.0",
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.connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE,
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.invert_polarity = false,
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};
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@ -649,7 +649,7 @@ void omap3_cm_save_scratchpad_contents(u32 *ptr)
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/*
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* As per erratum i671, ROM code does not respect the PER DPLL
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* programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
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* Then, in anycase, clear these bits to avoid extra latencies.
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* Then, in any case, clear these bits to avoid extra latencies.
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*/
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*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
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~OMAP3430_AUTO_PERIPH_DPLL_MASK;
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@ -257,18 +257,22 @@ extern void gic_dist_enable(void);
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extern bool gic_dist_disabled(void);
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extern void gic_timer_retrigger(void);
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extern void omap_smc1(u32 fn, u32 arg);
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extern void omap4_sar_ram_init(void);
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extern void __iomem *omap4_get_sar_ram_base(void);
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extern void omap4_mpuss_early_init(void);
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extern void omap_do_wfi(void);
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extern void omap4_secondary_startup(void);
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extern void omap4460_secondary_startup(void);
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#ifdef CONFIG_SMP
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/* Needed for secondary core boot */
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extern void omap4_secondary_startup(void);
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extern void omap4460_secondary_startup(void);
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extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
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extern void omap_auxcoreboot_addr(u32 cpu_addr);
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extern u32 omap_read_auxcoreboot0(void);
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extern void omap4_cpu_die(unsigned int cpu);
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extern int omap4_cpu_kill(unsigned int cpu);
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extern const struct smp_operations omap4_smp_ops;
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@ -29,7 +29,7 @@
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <video/omapdss.h>
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#include <linux/platform_data/omapdss.h>
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#include "omap_hwmod.h"
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#include "omap_device.h"
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#include "omap-pm.h"
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@ -33,4 +33,9 @@ int omap_init_vout(void);
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struct device_node * __init omapdss_find_dss_of_node(void);
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struct omap_dss_board_info;
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/* Init with the board info */
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int omap_display_init(struct omap_dss_board_info *board_data);
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#endif
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@ -27,7 +27,7 @@
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <video/omapdss.h>
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#include <linux/platform_data/omapdss.h>
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#include <video/omap-panel-data.h>
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#include "soc.h"
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@ -690,6 +690,8 @@ void __init omap4430_init_early(void)
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omap4xxx_check_revision();
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omap4xxx_check_features();
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omap2_prcm_base_init();
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omap4_sar_ram_init();
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omap4_mpuss_early_init();
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omap4_pm_init_early();
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omap44xx_voltagedomains_init();
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omap44xx_powerdomains_init();
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@ -718,6 +720,7 @@ void __init omap5_init_early(void)
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omap4_pm_init_early();
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omap2_prcm_base_init();
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omap5xxx_check_revision();
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omap4_sar_ram_init();
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omap54xx_voltagedomains_init();
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omap54xx_powerdomains_init();
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omap54xx_clockdomains_init();
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@ -34,18 +34,24 @@
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#include "cm3xxx.h"
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#include "cm-regbits-34xx.h"
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static struct clk *mcbsp_iclks[5];
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static int omap3_enable_st_clock(unsigned int id, bool enable)
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static int omap3_mcbsp_force_ick_on(struct clk *clk, bool force_on)
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{
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/*
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* Sidetone uses McBSP ICLK - which must not idle when sidetones
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* are enabled or sidetones start sounding ugly.
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*/
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if (enable)
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return omap2_clk_deny_idle(mcbsp_iclks[id]);
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if (!clk)
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return 0;
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if (force_on)
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return omap2_clk_deny_idle(clk);
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else
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return omap2_clk_allow_idle(mcbsp_iclks[id]);
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return omap2_clk_allow_idle(clk);
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}
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void __init omap3_mcbsp_init_pdata_callback(
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struct omap_mcbsp_platform_data *pdata)
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{
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if (!pdata)
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return;
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pdata->force_ick_on = omap3_mcbsp_force_ick_on;
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}
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static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
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@ -55,7 +61,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
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struct omap_hwmod *oh_device[2];
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struct omap_mcbsp_platform_data *pdata = NULL;
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struct platform_device *pdev;
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char clk_name[11];
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sscanf(oh->name, "mcbsp%d", &id);
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@ -96,9 +101,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
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if (oh->dev_attr) {
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oh_device[1] = omap_hwmod_lookup((
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(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
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pdata->enable_st_clock = omap3_enable_st_clock;
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sprintf(clk_name, "mcbsp%d_ick", id);
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mcbsp_iclks[id] = clk_get(NULL, clk_name);
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pdata->force_ick_on = omap3_mcbsp_force_ick_on;
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count++;
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}
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pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
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@ -1266,7 +1266,7 @@ static struct omap_ball __initdata omap3_cus_ball[] = {
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#endif
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/*
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* Signals different on CBB package comapared to superset
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* Signals different on CBB package compared to superset
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*/
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#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
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static struct omap_mux __initdata omap3_cbb_subset[] = {
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@ -1597,7 +1597,7 @@ static struct omap_ball __initdata omap3_cbb_ball[] = {
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#endif
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/*
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* Signals different on 36XX CBP package comapared to 34XX CBC package
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* Signals different on 36XX CBP package compared to 34XX CBC package
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*/
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#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
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static struct omap_mux __initdata omap36xx_cbp_subset[] = {
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@ -24,6 +24,16 @@
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#define AUX_CORE_BOOT0_PA 0x48281800
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#define API_HYP_ENTRY 0x102
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ENTRY(omap_secondary_startup)
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#ifdef CONFIG_SMP
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b secondary_startup
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#else
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/* Should never get here */
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again: wfi
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b again
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#endif
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#ENDPROC(omap_secondary_startup)
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/*
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* OMAP5 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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@ -39,7 +49,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
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and r4, r4, #0x0f
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cmp r0, r4
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bne wait
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b secondary_startup
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b omap_secondary_startup
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ENDPROC(omap5_secondary_startup)
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/*
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* Same as omap5_secondary_startup except we call into the ROM to
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@ -59,7 +69,7 @@ wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
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adr r0, hyp_boot
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smc #0
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hyp_boot:
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b secondary_startup
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b omap_secondary_startup
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ENDPROC(omap5_secondary_hyp_startup)
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/*
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* OMAP4 specific entry point for secondary CPU to jump from ROM
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@ -82,7 +92,7 @@ hold: ldr r12,=0x103
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* we've been released from the wait loop,secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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b omap_secondary_startup
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ENDPROC(omap4_secondary_startup)
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ENTRY(omap4460_secondary_startup)
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@ -119,5 +129,5 @@ hold_2: ldr r12,=0x103
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* we've been released from the wait loop,secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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b omap_secondary_startup
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ENDPROC(omap4460_secondary_startup)
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@ -64,3 +64,9 @@ void omap4_cpu_die(unsigned int cpu)
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pr_debug("CPU%u: spurious wakeup call\n", cpu);
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}
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}
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/* Needed by kexec and platform_can_cpu_hotplug() */
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int omap4_cpu_kill(unsigned int cpu)
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{
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return 1;
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}
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@ -62,6 +62,8 @@
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#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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static void __iomem *sar_base;
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|
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#ifdef CONFIG_SMP
|
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|
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struct omap4_cpu_pm_info {
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@ -90,7 +92,6 @@ struct cpu_pm_ops {
|
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|
||||
static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
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||||
static struct powerdomain *mpuss_pd;
|
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static void __iomem *sar_base;
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static u32 cpu_context_offset;
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||||
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||||
static int default_finish_suspend(unsigned long cpu_state)
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@ -366,9 +367,6 @@ int __init omap4_mpuss_init(void)
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||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (cpu_is_omap44xx())
|
||||
sar_base = omap4_get_sar_ram_base();
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||||
|
||||
/* Initilaise per CPU PM information */
|
||||
pm_info = &per_cpu(omap4_pm_info, 0x0);
|
||||
if (sar_base) {
|
||||
@ -444,3 +442,26 @@ int __init omap4_mpuss_init(void)
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to
|
||||
* current kernel's secondary_startup() early before
|
||||
* clockdomains_init(). Otherwise clockdomain_init() can
|
||||
* wake CPU1 and cause a hang.
|
||||
*/
|
||||
void __init omap4_mpuss_early_init(void)
|
||||
{
|
||||
unsigned long startup_pa;
|
||||
|
||||
if (!cpu_is_omap44xx())
|
||||
return;
|
||||
|
||||
sar_base = omap4_get_sar_ram_base();
|
||||
|
||||
if (cpu_is_omap443x())
|
||||
startup_pa = virt_to_phys(omap4_secondary_startup);
|
||||
else
|
||||
startup_pa = virt_to_phys(omap4460_secondary_startup);
|
||||
|
||||
writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
|
||||
}
|
||||
|
||||
@ -46,6 +46,7 @@
|
||||
|
||||
#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
|
||||
#define OMAP5_MON_AMBA_IF_INDEX 0x108
|
||||
#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
|
||||
|
||||
/* Secure PPA(Primary Protected Application) APIs */
|
||||
#define OMAP4_PPA_L2_POR_INDEX 0x23
|
||||
|
||||
@ -40,16 +40,70 @@
|
||||
|
||||
#define OMAP5_CORE_COUNT 0x2
|
||||
|
||||
/* SCU base address */
|
||||
static void __iomem *scu_base;
|
||||
struct omap_smp_config {
|
||||
unsigned long cpu1_rstctrl_pa;
|
||||
void __iomem *cpu1_rstctrl_va;
|
||||
void __iomem *scu_base;
|
||||
void *startup_addr;
|
||||
};
|
||||
|
||||
static struct omap_smp_config cfg;
|
||||
|
||||
static const struct omap_smp_config omap443x_cfg __initconst = {
|
||||
.cpu1_rstctrl_pa = 0x4824380c,
|
||||
.startup_addr = omap4_secondary_startup,
|
||||
};
|
||||
|
||||
static const struct omap_smp_config omap446x_cfg __initconst = {
|
||||
.cpu1_rstctrl_pa = 0x4824380c,
|
||||
.startup_addr = omap4460_secondary_startup,
|
||||
};
|
||||
|
||||
static const struct omap_smp_config omap5_cfg __initconst = {
|
||||
.cpu1_rstctrl_pa = 0x48243810,
|
||||
.startup_addr = omap5_secondary_startup,
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
void __iomem *omap4_get_scu_base(void)
|
||||
{
|
||||
return scu_base;
|
||||
return cfg.scu_base;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP5_ERRATA_801819
|
||||
void omap5_erratum_workaround_801819(void)
|
||||
{
|
||||
u32 acr, revidr;
|
||||
u32 acr_mask;
|
||||
|
||||
/* REVIDR[3] indicates erratum fix available on silicon */
|
||||
asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
|
||||
if (revidr & (0x1 << 3))
|
||||
return;
|
||||
|
||||
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
|
||||
/*
|
||||
* BIT(27) - Disables streaming. All write-allocate lines allocate in
|
||||
* the L1 or L2 cache.
|
||||
* BIT(25) - Disables streaming. All write-allocate lines allocate in
|
||||
* the L1 cache.
|
||||
*/
|
||||
acr_mask = (0x3 << 25) | (0x3 << 27);
|
||||
/* do we already have it done.. if yes, skip expensive smc */
|
||||
if ((acr & acr_mask) == acr_mask)
|
||||
return;
|
||||
|
||||
acr |= acr_mask;
|
||||
omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
|
||||
|
||||
pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
|
||||
__func__, smp_processor_id());
|
||||
}
|
||||
#else
|
||||
static inline void omap5_erratum_workaround_801819(void) { }
|
||||
#endif
|
||||
|
||||
static void omap4_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
@ -60,16 +114,19 @@ static void omap4_secondary_init(unsigned int cpu)
|
||||
* OMAP443X GP devices- SMP bit isn't accessible.
|
||||
* OMAP446X GP devices - SMP bit access is enabled on both CPUs.
|
||||
*/
|
||||
if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
|
||||
if (soc_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
|
||||
omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
|
||||
4, 0, 0, 0, 0, 0);
|
||||
|
||||
/*
|
||||
* Configure the CNTFRQ register for the secondary cpu's which
|
||||
* indicates the frequency of the cpu local timers.
|
||||
*/
|
||||
if (soc_is_omap54xx() || soc_is_dra7xx())
|
||||
if (soc_is_omap54xx() || soc_is_dra7xx()) {
|
||||
/*
|
||||
* Configure the CNTFRQ register for the secondary cpu's which
|
||||
* indicates the frequency of the cpu local timers.
|
||||
*/
|
||||
set_cntfreq();
|
||||
/* Configure ACR to disable streaming WA for 801819 */
|
||||
omap5_erratum_workaround_801819();
|
||||
}
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
@ -186,9 +243,9 @@ static void __init omap4_smp_init_cpus(void)
|
||||
* Currently we can't call ioremap here because
|
||||
* SoC detection won't work until after init_early.
|
||||
*/
|
||||
scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
|
||||
BUG_ON(!scu_base);
|
||||
ncores = scu_get_core_count(scu_base);
|
||||
cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
|
||||
BUG_ON(!cfg.scu_base);
|
||||
ncores = scu_get_core_count(cfg.scu_base);
|
||||
} else if (cpu_id == CPU_CORTEX_A15) {
|
||||
ncores = OMAP5_CORE_COUNT;
|
||||
}
|
||||
@ -206,18 +263,51 @@ static void __init omap4_smp_init_cpus(void)
|
||||
|
||||
static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
void *startup_addr = omap4_secondary_startup;
|
||||
void __iomem *base = omap_get_wakeupgen_base();
|
||||
const struct omap_smp_config *c = NULL;
|
||||
|
||||
if (soc_is_omap443x())
|
||||
c = &omap443x_cfg;
|
||||
else if (soc_is_omap446x())
|
||||
c = &omap446x_cfg;
|
||||
else if (soc_is_dra74x() || soc_is_omap54xx())
|
||||
c = &omap5_cfg;
|
||||
|
||||
if (!c) {
|
||||
pr_err("%s Unknown SMP SoC?\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Must preserve cfg.scu_base set earlier */
|
||||
cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa;
|
||||
cfg.startup_addr = c->startup_addr;
|
||||
|
||||
if (soc_is_dra74x() || soc_is_omap54xx()) {
|
||||
if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
|
||||
cfg.startup_addr = omap5_secondary_hyp_startup;
|
||||
omap5_erratum_workaround_801819();
|
||||
}
|
||||
|
||||
cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4);
|
||||
if (!cfg.cpu1_rstctrl_va)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Initialise the SCU and wake up the secondary core using
|
||||
* wakeup_secondary().
|
||||
*/
|
||||
if (scu_base)
|
||||
scu_enable(scu_base);
|
||||
if (cfg.scu_base)
|
||||
scu_enable(cfg.scu_base);
|
||||
|
||||
if (cpu_is_omap446x())
|
||||
startup_addr = omap4460_secondary_startup;
|
||||
/*
|
||||
* Reset CPU1 before configuring, otherwise kexec will
|
||||
* end up trying to use old kernel startup address.
|
||||
*/
|
||||
if (cfg.cpu1_rstctrl_va) {
|
||||
writel_relaxed(1, cfg.cpu1_rstctrl_va);
|
||||
readl_relaxed(cfg.cpu1_rstctrl_va);
|
||||
writel_relaxed(0, cfg.cpu1_rstctrl_va);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write the address of secondary startup routine into the
|
||||
@ -226,19 +316,10 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
||||
* A barrier is added to ensure that write buffer is drained
|
||||
*/
|
||||
if (omap_secure_apis_support())
|
||||
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
|
||||
omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr));
|
||||
else
|
||||
/*
|
||||
* If the boot CPU is in HYP mode then start secondary
|
||||
* CPU in HYP mode as well.
|
||||
*/
|
||||
if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
|
||||
writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
else
|
||||
writel_relaxed(virt_to_phys(omap5_secondary_startup),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
|
||||
writel_relaxed(virt_to_phys(cfg.startup_addr),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
}
|
||||
|
||||
const struct smp_operations omap4_smp_ops __initconst = {
|
||||
@ -248,5 +329,6 @@ const struct smp_operations omap4_smp_ops __initconst = {
|
||||
.smp_boot_secondary = omap4_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_die = omap4_cpu_die,
|
||||
.cpu_kill = omap4_cpu_kill,
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -61,7 +61,7 @@ static phys_addr_t dram_sync_paddr;
|
||||
static u32 dram_sync_size;
|
||||
|
||||
/*
|
||||
* The OMAP4 bus structure contains asynchrnous bridges which can buffer
|
||||
* The OMAP4 bus structure contains asynchronous bridges which can buffer
|
||||
* data writes from the MPU. These asynchronous bridges can be found on
|
||||
* paths between the MPU to EMIF, and the MPU to L3 interconnects.
|
||||
*
|
||||
@ -266,10 +266,11 @@ void __iomem *omap4_get_sar_ram_base(void)
|
||||
}
|
||||
|
||||
/*
|
||||
* SAR RAM used to save and restore the HW
|
||||
* context in low power modes
|
||||
* SAR RAM used to save and restore the HW context in low power modes.
|
||||
* Note that we need to initialize this very early for kexec. See
|
||||
* omap4_mpuss_early_init().
|
||||
*/
|
||||
static int __init omap4_sar_ram_init(void)
|
||||
void __init omap4_sar_ram_init(void)
|
||||
{
|
||||
unsigned long sar_base;
|
||||
|
||||
@ -282,16 +283,13 @@ static int __init omap4_sar_ram_init(void)
|
||||
else if (soc_is_omap54xx())
|
||||
sar_base = OMAP54XX_SAR_RAM_BASE;
|
||||
else
|
||||
return -ENOMEM;
|
||||
return;
|
||||
|
||||
/* Static mapping, never released */
|
||||
sar_ram_base = ioremap(sar_base, SZ_16K);
|
||||
if (WARN_ON(!sar_ram_base))
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
return;
|
||||
}
|
||||
omap_early_initcall(omap4_sar_ram_init);
|
||||
|
||||
static const struct of_device_id intc_match[] = {
|
||||
{ .compatible = "ti,omap4-wugen-mpu", },
|
||||
|
||||
@ -268,7 +268,7 @@ static int _omap_device_idle_hwmods(struct omap_device *od)
|
||||
* function returns a value different than the value the caller got
|
||||
* the last time it called this function.
|
||||
*
|
||||
* If any hwmods exist for the omap_device assoiated with @pdev,
|
||||
* If any hwmods exist for the omap_device associated with @pdev,
|
||||
* return the context loss counter for that hwmod, otherwise return
|
||||
* zero.
|
||||
*/
|
||||
|
||||
@ -36,17 +36,8 @@ extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio3;
|
||||
extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2;
|
||||
extern struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3;
|
||||
@ -98,17 +89,8 @@ extern struct omap_hwmod am33xx_dcan0_hwmod;
|
||||
extern struct omap_hwmod am33xx_dcan1_hwmod;
|
||||
extern struct omap_hwmod am33xx_elm_hwmod;
|
||||
extern struct omap_hwmod am33xx_epwmss0_hwmod;
|
||||
extern struct omap_hwmod am33xx_ecap0_hwmod;
|
||||
extern struct omap_hwmod am33xx_eqep0_hwmod;
|
||||
extern struct omap_hwmod am33xx_ehrpwm0_hwmod;
|
||||
extern struct omap_hwmod am33xx_epwmss1_hwmod;
|
||||
extern struct omap_hwmod am33xx_ecap1_hwmod;
|
||||
extern struct omap_hwmod am33xx_eqep1_hwmod;
|
||||
extern struct omap_hwmod am33xx_ehrpwm1_hwmod;
|
||||
extern struct omap_hwmod am33xx_epwmss2_hwmod;
|
||||
extern struct omap_hwmod am33xx_ecap2_hwmod;
|
||||
extern struct omap_hwmod am33xx_eqep2_hwmod;
|
||||
extern struct omap_hwmod am33xx_ehrpwm2_hwmod;
|
||||
extern struct omap_hwmod am33xx_gpio1_hwmod;
|
||||
extern struct omap_hwmod am33xx_gpio2_hwmod;
|
||||
extern struct omap_hwmod am33xx_gpio3_hwmod;
|
||||
|
||||
@ -176,28 +176,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
|
||||
.master = &am33xx_epwmss0_hwmod,
|
||||
.slave = &am33xx_ecap0_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
|
||||
.master = &am33xx_epwmss0_hwmod,
|
||||
.slave = &am33xx_eqep0_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
|
||||
.master = &am33xx_epwmss0_hwmod,
|
||||
.slave = &am33xx_ehrpwm0_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
||||
static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48302000,
|
||||
@ -215,27 +193,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
|
||||
.master = &am33xx_epwmss1_hwmod,
|
||||
.slave = &am33xx_ecap1_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
|
||||
.master = &am33xx_epwmss1_hwmod,
|
||||
.slave = &am33xx_eqep1_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
|
||||
.master = &am33xx_epwmss1_hwmod,
|
||||
.slave = &am33xx_ehrpwm1_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48304000,
|
||||
@ -253,27 +210,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
|
||||
.master = &am33xx_epwmss2_hwmod,
|
||||
.slave = &am33xx_ecap2_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
|
||||
.master = &am33xx_epwmss2_hwmod,
|
||||
.slave = &am33xx_eqep2_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
|
||||
.master = &am33xx_epwmss2_hwmod,
|
||||
.slave = &am33xx_ehrpwm2_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3s cfg -> gpmc */
|
||||
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
|
||||
.master = &am33xx_l3_s_hwmod,
|
||||
|
||||
@ -449,18 +449,6 @@ struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
|
||||
.sysc = &am33xx_epwmss_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
|
||||
.name = "ecap",
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
|
||||
.name = "eqep",
|
||||
};
|
||||
|
||||
struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
|
||||
.name = "ehrpwm",
|
||||
};
|
||||
|
||||
/* epwmss0 */
|
||||
struct omap_hwmod am33xx_epwmss0_hwmod = {
|
||||
.name = "epwmss0",
|
||||
@ -474,30 +462,6 @@ struct omap_hwmod am33xx_epwmss0_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
/* ecap0 */
|
||||
struct omap_hwmod am33xx_ecap0_hwmod = {
|
||||
.name = "ecap0",
|
||||
.class = &am33xx_ecap_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/* eqep0 */
|
||||
struct omap_hwmod am33xx_eqep0_hwmod = {
|
||||
.name = "eqep0",
|
||||
.class = &am33xx_eqep_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/* ehrpwm0 */
|
||||
struct omap_hwmod am33xx_ehrpwm0_hwmod = {
|
||||
.name = "ehrpwm0",
|
||||
.class = &am33xx_ehrpwm_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/* epwmss1 */
|
||||
struct omap_hwmod am33xx_epwmss1_hwmod = {
|
||||
.name = "epwmss1",
|
||||
@ -511,30 +475,6 @@ struct omap_hwmod am33xx_epwmss1_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
/* ecap1 */
|
||||
struct omap_hwmod am33xx_ecap1_hwmod = {
|
||||
.name = "ecap1",
|
||||
.class = &am33xx_ecap_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/* eqep1 */
|
||||
struct omap_hwmod am33xx_eqep1_hwmod = {
|
||||
.name = "eqep1",
|
||||
.class = &am33xx_eqep_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/* ehrpwm1 */
|
||||
struct omap_hwmod am33xx_ehrpwm1_hwmod = {
|
||||
.name = "ehrpwm1",
|
||||
.class = &am33xx_ehrpwm_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/* epwmss2 */
|
||||
struct omap_hwmod am33xx_epwmss2_hwmod = {
|
||||
.name = "epwmss2",
|
||||
@ -548,30 +488,6 @@ struct omap_hwmod am33xx_epwmss2_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
/* ecap2 */
|
||||
struct omap_hwmod am33xx_ecap2_hwmod = {
|
||||
.name = "ecap2",
|
||||
.class = &am33xx_ecap_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/* eqep2 */
|
||||
struct omap_hwmod am33xx_eqep2_hwmod = {
|
||||
.name = "eqep2",
|
||||
.class = &am33xx_eqep_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/* ehrpwm2 */
|
||||
struct omap_hwmod am33xx_ehrpwm2_hwmod = {
|
||||
.name = "ehrpwm2",
|
||||
.class = &am33xx_ehrpwm_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
/*
|
||||
* 'gpio' class: for gpio 0,1,2,3
|
||||
*/
|
||||
@ -1476,6 +1392,7 @@ static void omap_hwmod_am43xx_rst(void)
|
||||
{
|
||||
RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
|
||||
RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
|
||||
RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
|
||||
RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
|
||||
}
|
||||
|
||||
|
||||
@ -593,17 +593,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&am33xx_l4_ls__spinlock,
|
||||
&am33xx_l4_ls__elm,
|
||||
&am33xx_l4_ls__epwmss0,
|
||||
&am33xx_epwmss0__ecap0,
|
||||
&am33xx_epwmss0__eqep0,
|
||||
&am33xx_epwmss0__ehrpwm0,
|
||||
&am33xx_l4_ls__epwmss1,
|
||||
&am33xx_epwmss1__ecap1,
|
||||
&am33xx_epwmss1__eqep1,
|
||||
&am33xx_epwmss1__ehrpwm1,
|
||||
&am33xx_l4_ls__epwmss2,
|
||||
&am33xx_epwmss2__ecap2,
|
||||
&am33xx_epwmss2__eqep2,
|
||||
&am33xx_epwmss2__ehrpwm2,
|
||||
&am33xx_l3_s__gpmc,
|
||||
&am33xx_l3_main__lcdc,
|
||||
&am33xx_l4_ls__mcspi0,
|
||||
|
||||
@ -1322,16 +1322,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
|
||||
.name = "mcbsp2_sidetone",
|
||||
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
|
||||
.main_clk = "mcbsp2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP3430_EN_MCBSP2_SHIFT,
|
||||
.module_offs = OMAP3430_PER_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
|
||||
},
|
||||
},
|
||||
.main_clk = "mcbsp2_ick",
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* mcbsp3_sidetone */
|
||||
@ -1344,16 +1336,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
|
||||
.name = "mcbsp3_sidetone",
|
||||
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
|
||||
.main_clk = "mcbsp3_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP3430_EN_MCBSP3_SHIFT,
|
||||
.module_offs = OMAP3430_PER_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
|
||||
},
|
||||
},
|
||||
.main_clk = "mcbsp3_ick",
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* SR common */
|
||||
|
||||
@ -202,13 +202,6 @@ static struct omap_hwmod am43xx_epwmss3_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
|
||||
.name = "ehrpwm3",
|
||||
.class = &am33xx_ehrpwm_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am43xx_epwmss4_hwmod = {
|
||||
.name = "epwmss4",
|
||||
.class = &am33xx_epwmss_hwmod_class,
|
||||
@ -222,13 +215,6 @@ static struct omap_hwmod am43xx_epwmss4_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
|
||||
.name = "ehrpwm4",
|
||||
.class = &am33xx_ehrpwm_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am43xx_epwmss5_hwmod = {
|
||||
.name = "epwmss5",
|
||||
.class = &am33xx_epwmss_hwmod_class,
|
||||
@ -242,13 +228,6 @@ static struct omap_hwmod am43xx_epwmss5_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
|
||||
.name = "ehrpwm5",
|
||||
.class = &am33xx_ehrpwm_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am43xx_spi2_hwmod = {
|
||||
.name = "spi2",
|
||||
.class = &am33xx_spi_hwmod_class,
|
||||
@ -744,13 +723,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
|
||||
.master = &am43xx_epwmss3_hwmod,
|
||||
.slave = &am43xx_ehrpwm3_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
|
||||
.master = &am33xx_l4_ls_hwmod,
|
||||
.slave = &am43xx_epwmss4_hwmod,
|
||||
@ -758,13 +730,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
|
||||
.master = &am43xx_epwmss4_hwmod,
|
||||
.slave = &am43xx_ehrpwm4_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
|
||||
.master = &am33xx_l4_ls_hwmod,
|
||||
.slave = &am43xx_epwmss5_hwmod,
|
||||
@ -772,13 +737,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
|
||||
.master = &am43xx_epwmss5_hwmod,
|
||||
.slave = &am43xx_ehrpwm5_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
|
||||
.master = &am33xx_l4_ls_hwmod,
|
||||
.slave = &am43xx_spi2_hwmod,
|
||||
@ -919,11 +877,8 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&am43xx_l4_ls__timer10,
|
||||
&am43xx_l4_ls__timer11,
|
||||
&am43xx_l4_ls__epwmss3,
|
||||
&am43xx_epwmss3__ehrpwm3,
|
||||
&am43xx_l4_ls__epwmss4,
|
||||
&am43xx_epwmss4__ehrpwm4,
|
||||
&am43xx_l4_ls__epwmss5,
|
||||
&am43xx_epwmss5__ehrpwm5,
|
||||
&am43xx_l4_ls__mcspi2,
|
||||
&am43xx_l4_ls__mcspi3,
|
||||
&am43xx_l4_ls__mcspi4,
|
||||
@ -982,17 +937,8 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&am33xx_l4_ls__spinlock,
|
||||
&am33xx_l4_ls__elm,
|
||||
&am33xx_l4_ls__epwmss0,
|
||||
&am33xx_epwmss0__ecap0,
|
||||
&am33xx_epwmss0__eqep0,
|
||||
&am33xx_epwmss0__ehrpwm0,
|
||||
&am33xx_l4_ls__epwmss1,
|
||||
&am33xx_epwmss1__ecap1,
|
||||
&am33xx_epwmss1__eqep1,
|
||||
&am33xx_epwmss1__ehrpwm1,
|
||||
&am33xx_l4_ls__epwmss2,
|
||||
&am33xx_epwmss2__ecap2,
|
||||
&am33xx_epwmss2__eqep2,
|
||||
&am33xx_epwmss2__ehrpwm2,
|
||||
&am33xx_l3_s__gpmc,
|
||||
&am33xx_l4_ls__mcspi0,
|
||||
&am33xx_l4_ls__mcspi1,
|
||||
|
||||
@ -2905,58 +2905,27 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
|
||||
{
|
||||
.name = "family",
|
||||
.pa_start = 0x58000000,
|
||||
.pa_end = 0x5800007f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_1 -> dss */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_dss_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.addr = dra7xx_dss_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
|
||||
{
|
||||
.name = "dispc",
|
||||
.pa_start = 0x58001000,
|
||||
.pa_end = 0x58001fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_1 -> dispc */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_dss_dispc_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.addr = dra7xx_dss_dispc_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
|
||||
{
|
||||
.name = "hdmi_wp",
|
||||
.pa_start = 0x58040000,
|
||||
.pa_end = 0x580400ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_1 -> dispc */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_dss_hdmi_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.addr = dra7xx_dss_hdmi_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -3410,21 +3379,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4b300000,
|
||||
.pa_end = 0x4b30007f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_1 -> qspi */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_qspi_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.addr = dra7xx_qspi_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
||||
@ -243,7 +243,7 @@ static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
|
||||
.sysc = &ti81xx_rtc_sysc,
|
||||
};
|
||||
|
||||
struct omap_hwmod ti81xx_rtc_hwmod = {
|
||||
static struct omap_hwmod ti81xx_rtc_hwmod = {
|
||||
.name = "rtc",
|
||||
.class = &ti81xx_rtc_hwmod_class,
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
|
||||
@ -26,6 +26,7 @@
|
||||
#include <linux/platform_data/wkup_m3.h>
|
||||
#include <linux/platform_data/pwm_omap_dmtimer.h>
|
||||
#include <linux/platform_data/media/ir-rx51.h>
|
||||
#include <linux/platform_data/asoc-ti-mcbsp.h>
|
||||
#include <plat/dmtimer.h>
|
||||
|
||||
#include "common.h"
|
||||
@ -505,6 +506,16 @@ static struct platform_device __maybe_unused rx51_lirc_device = {
|
||||
},
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_OMAP_SOC_MCBSP)
|
||||
static struct omap_mcbsp_platform_data mcbsp_pdata;
|
||||
static void __init omap3_mcbsp_init(void)
|
||||
{
|
||||
omap3_mcbsp_init_pdata_callback(&mcbsp_pdata);
|
||||
}
|
||||
#else
|
||||
static void __init omap3_mcbsp_init(void) {}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Few boards still need auxdata populated before we populate
|
||||
* the dev entries in of_platform_populate().
|
||||
@ -536,6 +547,11 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
|
||||
OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
|
||||
&am35xx_emac_pdata),
|
||||
/* McBSP modules with sidetone core */
|
||||
#if IS_ENABLED(CONFIG_SND_OMAP_SOC_MCBSP)
|
||||
OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49022000, "49022000.mcbsp", &mcbsp_pdata),
|
||||
OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49024000, "49024000.mcbsp", &mcbsp_pdata),
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
OF_DEV_AUXDATA("ti,am3352-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
|
||||
@ -608,6 +624,8 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
|
||||
of_machine_is_compatible("ti,omap3"))
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
|
||||
if (of_machine_is_compatible("ti,omap3"))
|
||||
omap3_mcbsp_init();
|
||||
pdata_quirks_check(auxdata_quirks);
|
||||
of_platform_populate(NULL, omap_dt_match_table,
|
||||
omap_auxdata_lookup, NULL);
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
|
||||
/* RM RSTST offsets */
|
||||
#define AM43XX_RM_GFX_RSTST_OFFSET 0x0014
|
||||
#define AM43XX_RM_PER_RSTST_OFFSET 0x0014
|
||||
#define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014
|
||||
|
||||
/* CM instances */
|
||||
|
||||
@ -52,8 +52,6 @@
|
||||
/* PRM.PER_PRM register offsets */
|
||||
#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000
|
||||
#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
|
||||
#define AM33XX_RM_PER_RSTST_OFFSET 0x0004
|
||||
#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
|
||||
#define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
|
||||
#define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
|
||||
#define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c
|
||||
|
||||
@ -175,8 +175,8 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
|
||||
* don't adjust it down as your clock period increases the refresh interval
|
||||
* will not be met. Setting all parameters for complete worst case may work,
|
||||
* but may cut memory performance by 2x. Due to errata the DLLs need to be
|
||||
* unlocked and their value needs run time calibration. A dynamic call is
|
||||
* need for that as no single right value exists acorss production samples.
|
||||
* unlocked and their value needs run time calibration. A dynamic call is
|
||||
* need for that as no single right value exists across production samples.
|
||||
*
|
||||
* Only the FULL speed values are given. Current code is such that rate
|
||||
* changes must be made at DPLLoutx2. The actual value adjustment for low
|
||||
|
||||
@ -108,6 +108,9 @@ static struct ti_dt_clk am33xx_clks[] = {
|
||||
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
|
||||
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
|
||||
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
|
||||
DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"),
|
||||
DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"),
|
||||
DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
|
||||
@ -115,6 +115,12 @@ static struct ti_dt_clk am43xx_clks[] = {
|
||||
DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
|
||||
DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
|
||||
DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
|
||||
DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"),
|
||||
DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"),
|
||||
DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"),
|
||||
DT_CLK("48306200.pwm", "tbclk", "ehrpwm3_tbclk"),
|
||||
DT_CLK("48308200.pwm", "tbclk", "ehrpwm4_tbclk"),
|
||||
DT_CLK("4830a200.pwm", "tbclk", "ehrpwm5_tbclk"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
|
||||
@ -44,7 +44,7 @@ struct omap_mcbsp_platform_data {
|
||||
/* McBSP platform and instance specific features */
|
||||
bool has_wakeup; /* Wakeup capability */
|
||||
bool has_ccr; /* Transceiver has configuration control registers */
|
||||
int (*enable_st_clock)(unsigned int, bool);
|
||||
int (*force_ick_on)(struct clk *clk, bool force_on);
|
||||
};
|
||||
|
||||
/**
|
||||
@ -55,4 +55,6 @@ struct omap_mcbsp_dev_attr {
|
||||
const char *sidetone;
|
||||
};
|
||||
|
||||
void omap3_mcbsp_init_pdata_callback(struct omap_mcbsp_platform_data *pdata);
|
||||
|
||||
#endif
|
||||
|
||||
42
include/linux/platform_data/omapdss.h
Normal file
42
include/linux/platform_data/omapdss.h
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __OMAPDSS_PDATA_H
|
||||
#define __OMAPDSS_PDATA_H
|
||||
|
||||
enum omapdss_version {
|
||||
OMAPDSS_VER_UNKNOWN = 0,
|
||||
OMAPDSS_VER_OMAP24xx,
|
||||
OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
|
||||
OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
|
||||
OMAPDSS_VER_OMAP3630,
|
||||
OMAPDSS_VER_AM35xx,
|
||||
OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
|
||||
OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
|
||||
OMAPDSS_VER_OMAP4, /* All other OMAP4s */
|
||||
OMAPDSS_VER_OMAP5,
|
||||
OMAPDSS_VER_AM43xx,
|
||||
OMAPDSS_VER_DRA7xx,
|
||||
};
|
||||
|
||||
struct omap_dss_device;
|
||||
|
||||
/* Board specific data */
|
||||
struct omap_dss_board_info {
|
||||
int num_devices;
|
||||
struct omap_dss_device **devices;
|
||||
struct omap_dss_device *default_device;
|
||||
const char *default_display_name;
|
||||
int (*dsi_enable_pads)(int dsi_id, unsigned int lane_mask);
|
||||
void (*dsi_disable_pads)(int dsi_id, unsigned int lane_mask);
|
||||
int (*set_min_bus_tput)(struct device *dev, unsigned long r);
|
||||
enum omapdss_version version;
|
||||
};
|
||||
|
||||
#endif /* __OMAPDSS_PDATA_H */
|
||||
@ -22,6 +22,7 @@
|
||||
#include <linux/kobject.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_data/omapdss.h>
|
||||
|
||||
#include <video/videomode.h>
|
||||
|
||||
@ -303,36 +304,6 @@ struct omap_dss_dsi_config {
|
||||
enum omap_dss_dsi_trans_mode trans_mode;
|
||||
};
|
||||
|
||||
enum omapdss_version {
|
||||
OMAPDSS_VER_UNKNOWN = 0,
|
||||
OMAPDSS_VER_OMAP24xx,
|
||||
OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
|
||||
OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
|
||||
OMAPDSS_VER_OMAP3630,
|
||||
OMAPDSS_VER_AM35xx,
|
||||
OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
|
||||
OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
|
||||
OMAPDSS_VER_OMAP4, /* All other OMAP4s */
|
||||
OMAPDSS_VER_OMAP5,
|
||||
OMAPDSS_VER_AM43xx,
|
||||
OMAPDSS_VER_DRA7xx,
|
||||
};
|
||||
|
||||
/* Board specific data */
|
||||
struct omap_dss_board_info {
|
||||
int num_devices;
|
||||
struct omap_dss_device **devices;
|
||||
struct omap_dss_device *default_device;
|
||||
const char *default_display_name;
|
||||
int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
|
||||
void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
|
||||
int (*set_min_bus_tput)(struct device *dev, unsigned long r);
|
||||
enum omapdss_version version;
|
||||
};
|
||||
|
||||
/* Init with the board info */
|
||||
extern int omap_display_init(struct omap_dss_board_info *board_data);
|
||||
|
||||
struct omap_video_timings {
|
||||
/* Unit: pixels */
|
||||
u16 x_res;
|
||||
|
||||
@ -257,8 +257,8 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
|
||||
{
|
||||
unsigned int w;
|
||||
|
||||
if (mcbsp->pdata->enable_st_clock)
|
||||
mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
|
||||
if (mcbsp->pdata->force_ick_on)
|
||||
mcbsp->pdata->force_ick_on(mcbsp->st_data->mcbsp_iclk, true);
|
||||
|
||||
/* Disable Sidetone clock auto-gating for normal operation */
|
||||
w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
|
||||
@ -287,8 +287,8 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
|
||||
w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
|
||||
MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
|
||||
|
||||
if (mcbsp->pdata->enable_st_clock)
|
||||
mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
|
||||
if (mcbsp->pdata->force_ick_on)
|
||||
mcbsp->pdata->force_ick_on(mcbsp->st_data->mcbsp_iclk, false);
|
||||
}
|
||||
|
||||
static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
|
||||
@ -946,6 +946,13 @@ static int omap_st_add(struct omap_mcbsp *mcbsp, struct resource *res)
|
||||
if (!st_data)
|
||||
return -ENOMEM;
|
||||
|
||||
st_data->mcbsp_iclk = clk_get(mcbsp->dev, "ick");
|
||||
if (IS_ERR(st_data->mcbsp_iclk)) {
|
||||
dev_warn(mcbsp->dev,
|
||||
"Failed to get ick, sidetone might be broken\n");
|
||||
st_data->mcbsp_iclk = NULL;
|
||||
}
|
||||
|
||||
st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
|
||||
resource_size(res));
|
||||
if (!st_data->io_base_st)
|
||||
@ -1088,11 +1095,13 @@ err_thres:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
|
||||
void omap_mcbsp_cleanup(struct omap_mcbsp *mcbsp)
|
||||
{
|
||||
if (mcbsp->pdata->buffer_size)
|
||||
sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
|
||||
|
||||
if (mcbsp->st_data)
|
||||
if (mcbsp->st_data) {
|
||||
sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
|
||||
clk_put(mcbsp->st_data->mcbsp_iclk);
|
||||
}
|
||||
}
|
||||
|
||||
@ -280,6 +280,7 @@ struct omap_mcbsp_reg_cfg {
|
||||
|
||||
struct omap_mcbsp_st_data {
|
||||
void __iomem *io_base_st;
|
||||
struct clk *mcbsp_iclk;
|
||||
bool running;
|
||||
bool enabled;
|
||||
s16 taps[128]; /* Sidetone filter coefficients */
|
||||
@ -349,6 +350,6 @@ int omap_st_disable(struct omap_mcbsp *mcbsp);
|
||||
int omap_st_is_enabled(struct omap_mcbsp *mcbsp);
|
||||
|
||||
int omap_mcbsp_init(struct platform_device *pdev);
|
||||
void omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp);
|
||||
void omap_mcbsp_cleanup(struct omap_mcbsp *mcbsp);
|
||||
|
||||
#endif /* __ASOC_MCBSP_H */
|
||||
|
||||
@ -788,6 +788,7 @@ static int asoc_mcbsp_probe(struct platform_device *pdev)
|
||||
match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
|
||||
if (match) {
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct omap_mcbsp_platform_data *pdata_quirk = pdata;
|
||||
int buffer_size;
|
||||
|
||||
pdata = devm_kzalloc(&pdev->dev,
|
||||
@ -799,6 +800,8 @@ static int asoc_mcbsp_probe(struct platform_device *pdev)
|
||||
memcpy(pdata, match->data, sizeof(*pdata));
|
||||
if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
|
||||
pdata->buffer_size = buffer_size;
|
||||
if (pdata_quirk)
|
||||
pdata->force_ick_on = pdata_quirk->force_ick_on;
|
||||
} else if (!pdata) {
|
||||
dev_err(&pdev->dev, "missing platform data.\n");
|
||||
return -EINVAL;
|
||||
@ -832,7 +835,7 @@ static int asoc_mcbsp_remove(struct platform_device *pdev)
|
||||
if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
|
||||
mcbsp->pdata->ops->free(mcbsp->id);
|
||||
|
||||
omap_mcbsp_sysfs_remove(mcbsp);
|
||||
omap_mcbsp_cleanup(mcbsp);
|
||||
|
||||
clk_put(mcbsp->fclk);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user