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KVM: arm/arm64: vgic-v2: Always resample level interrupts

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When reading back from the list registers, we need to perform
two actions for level interrupts:
1) clear the soft-pending bit if the interrupt is not pending
   anymore *in the list register*
2) resample the line level and propagate it to the pending state

But these two actions shouldn't be linked, and we should *always*
resample the line level, no matter what state is in the list
register. Otherwise, we may end-up injecting spurious interrupts
that have been already retired.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
This commit is contained in:
Marc Zyngier 2016-05-25 15:26:35 +01:00 committed by Christoffer Dall
parent fa89c77e89
commit df7942d17e
1 changed files with 9 additions and 5 deletions
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14
virt/kvm/arm/vgic/vgic-v2.c
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@ -112,11 +112,15 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
}
}
/* Clear soft pending state when level IRQs have been acked */
if (irq->config == VGIC_CONFIG_LEVEL &&
!(val & GICH_LR_PENDING_BIT)) {
irq->soft_pending = false;
irq->pending = irq->line_level;
/*
* Clear soft pending state when level irqs have been acked.
* Always regenerate the pending state.
*/
if (irq->config == VGIC_CONFIG_LEVEL) {
if (!(val & GICH_LR_PENDING_BIT))
irq->soft_pending = false;
irq->pending = irq->line_level || irq->soft_pending;
}
spin_unlock(&irq->irq_lock);