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Merge remote branch 'nouveau/for-airlied' into drm-next

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* nouveau/for-airlied:
  drm/nouveau: fix i2c-related init table handlers
  drm/nouveau: support init table i2c device identifier 0x81
  drm/nouveau: ensure we've parsed i2c table entry for INIT_*I2C* handlers
  drm/nouveau: display error message for any failed init table opcode
  drm/nouveau: fix init table handlers to return proper error codes
  drm/nv50: support fractional feedback divider on newer chips
  drm/nv50: fix monitor detection on certain chipsets
  drm/nv50: store full dcb i2c entry from vbios
  drm/nv50: fix suspend/resume with DP outputs
  drm/nv50: output calculated crtc pll when debugging on
  drm/nouveau: dump pll limits entries when debugging is on
  drm/nouveau: bios parser fixes for eDP boards
  drm/nouveau: fix a nouveau_bo dereference after it's been destroyed
  drm/nv40: remove some completed ctxprog TODOs
  drm/nv04: Implement missing nv04 PGRAPH methods in software.
  drm/nouveau: Use 0x5f instead of 0x9f as imageblit on original NV10.
This commit is contained in:
Dave Airlie 2010-05-21 15:44:32 +10:00
commit df696a6fe8
15 changed files with 1066 additions and 222 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/nouveau/Makefile
View File

@ -22,7 +22,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
nv50_cursor.o nv50_display.o nv50_fbcon.o \
nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \
nv17_gpio.o nv50_gpio.o
nv17_gpio.o nv50_gpio.o \
nv50_calc.o
nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o

498
drivers/gpu/drm/nouveau/nouveau_bios.c
View File

@ -26,6 +26,7 @@
#define NV_DEBUG_NOTRACE
#include "nouveau_drv.h"
#include "nouveau_hw.h"
#include "nouveau_encoder.h"
/* these defines are made up */
#define NV_CIO_CRE_44_HEADA 0x0
@ -256,6 +257,11 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
struct init_tbl_entry {
char *name;
uint8_t id;
/* Return:
* > 0: success, length of opcode
* 0: success, but abort further parsing of table (INIT_DONE etc)
* < 0: failure, table parsing will be aborted
*/
int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
};
@ -709,6 +715,83 @@ static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
return dcb_entry;
}
static int
read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
{
uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
int recordoffset = 0, rdofs = 1, wrofs = 0;
uint8_t port_type = 0;
if (!i2ctable)
return -EINVAL;
if (dcb_version >= 0x30) {
if (i2ctable[0] != dcb_version) /* necessary? */
NV_WARN(dev,
"DCB I2C table version mismatch (%02X vs %02X)\n",
i2ctable[0], dcb_version);
dcb_i2c_ver = i2ctable[0];
headerlen = i2ctable[1];
if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
i2c_entries = i2ctable[2];
else
NV_WARN(dev,
"DCB I2C table has more entries than indexable "
"(%d entries, max %d)\n", i2ctable[2],
DCB_MAX_NUM_I2C_ENTRIES);
entry_len = i2ctable[3];
/* [4] is i2c_default_indices, read in parse_dcb_table() */
}
/*
* It's your own fault if you call this function on a DCB 1.1 BIOS --
* the test below is for DCB 1.2
*/
if (dcb_version < 0x14) {
recordoffset = 2;
rdofs = 0;
wrofs = 1;
}
if (index == 0xf)
return 0;
if (index >= i2c_entries) {
NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
index, i2ctable[2]);
return -ENOENT;
}
if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
NV_ERROR(dev, "DCB I2C entry invalid\n");
return -EINVAL;
}
if (dcb_i2c_ver >= 0x30) {
port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
/*
* Fixup for chips using same address offset for read and
* write.
*/
if (port_type == 4) /* seen on C51 */
rdofs = wrofs = 1;
if (port_type >= 5) /* G80+ */
rdofs = wrofs = 0;
}
if (dcb_i2c_ver >= 0x40) {
if (port_type != 5 && port_type != 6)
NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
}
i2c->port_type = port_type;
i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
return 0;
}
static struct nouveau_i2c_chan *
init_i2c_device_find(struct drm_device *dev, int i2c_index)
{
@ -727,6 +810,20 @@ init_i2c_device_find(struct drm_device *dev, int i2c_index)
}
if (i2c_index == 0x80) /* g80+ */
i2c_index = dcb->i2c_default_indices & 0xf;
else
if (i2c_index == 0x81)
i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
if (i2c_index > DCB_MAX_NUM_I2C_ENTRIES) {
NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
return NULL;
}
/* Make sure i2c table entry has been parsed, it may not
* have been if this is a bus not referenced by a DCB encoder
*/
read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
i2c_index, &dcb->i2c[i2c_index]);
return nouveau_i2c_find(dev, i2c_index);
}
@ -818,7 +915,7 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
NV_ERROR(bios->dev,
"0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
offset, config, count);
return 0;
return -EINVAL;
}
configval = ROM32(bios->data[offset + 11 + config * 4]);
@ -920,7 +1017,7 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
NV_ERROR(bios->dev,
"0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
offset, config, count);
return 0;
return -EINVAL;
}
freq = ROM16(bios->data[offset + 12 + config * 2]);
@ -1066,6 +1163,126 @@ init_io_flag_condition(struct nvbios *bios, uint16_t offset,
return 2;
}
static int
init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
/*
* INIT_DP_CONDITION opcode: 0x3A ('')
*
* offset (8 bit): opcode
* offset + 1 (8 bit): "sub" opcode
* offset + 2 (8 bit): unknown
*
*/
struct bit_displayport_encoder_table *dpe = NULL;
struct dcb_entry *dcb = bios->display.output;
struct drm_device *dev = bios->dev;
uint8_t cond = bios->data[offset + 1];
int dummy;
BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
if (!iexec->execute)
return 3;
dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
if (!dpe) {
NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
return -EINVAL;
}
switch (cond) {
case 0:
{
struct dcb_connector_table_entry *ent =
&bios->dcb.connector.entry[dcb->connector];
if (ent->type != DCB_CONNECTOR_eDP)
iexec->execute = false;
}
break;
case 1:
case 2:
if (!(dpe->unknown & cond))
iexec->execute = false;
break;
case 5:
{
struct nouveau_i2c_chan *auxch;
int ret;
auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
if (!auxch)
return -ENODEV;
ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
if (ret)
return ret;
if (cond & 1)
iexec->execute = false;
}
break;
default:
NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
break;
}
if (iexec->execute)
BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
else
BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
return 3;
}
static int
init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
/*
* INIT_3B opcode: 0x3B ('')
*
* offset (8 bit): opcode
* offset + 1 (8 bit): crtc index
*
*/
uint8_t or = ffs(bios->display.output->or) - 1;
uint8_t index = bios->data[offset + 1];
uint8_t data;
if (!iexec->execute)
return 2;
data = bios_idxprt_rd(bios, 0x3d4, index);
bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
return 2;
}
static int
init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
/*
* INIT_3C opcode: 0x3C ('')
*
* offset (8 bit): opcode
* offset + 1 (8 bit): crtc index
*
*/
uint8_t or = ffs(bios->display.output->or) - 1;
uint8_t index = bios->data[offset + 1];
uint8_t data;
if (!iexec->execute)
return 2;
data = bios_idxprt_rd(bios, 0x3d4, index);
bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
return 2;
}
static int
init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
struct init_exec *iexec)
@ -1170,7 +1387,7 @@ init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
NV_ERROR(bios->dev,
"0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
offset, config, count);
return 0;
return -EINVAL;
}
freq = ROM32(bios->data[offset + 11 + config * 4]);
@ -1231,12 +1448,11 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
*/
uint8_t i2c_index = bios->data[offset + 1];
uint8_t i2c_address = bios->data[offset + 2];
uint8_t i2c_address = bios->data[offset + 2] >> 1;
uint8_t count = bios->data[offset + 3];
int len = 4 + count * 3;
struct nouveau_i2c_chan *chan;
struct i2c_msg msg;
int i;
int len = 4 + count * 3;
int ret, i;
if (!iexec->execute)
return len;
@ -1247,35 +1463,34 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
chan = init_i2c_device_find(bios->dev, i2c_index);
if (!chan)
return 0;
return -ENODEV;
for (i = 0; i < count; i++) {
uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
uint8_t reg = bios->data[offset + 4 + i * 3];
uint8_t mask = bios->data[offset + 5 + i * 3];
uint8_t data = bios->data[offset + 6 + i * 3];
uint8_t value;
union i2c_smbus_data val;
msg.addr = i2c_address;
msg.flags = I2C_M_RD;
msg.len = 1;
msg.buf = &value;
if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
return 0;
ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
I2C_SMBUS_READ, reg,
I2C_SMBUS_BYTE_DATA, &val);
if (ret < 0)
return ret;
BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
"Mask: 0x%02X, Data: 0x%02X\n",
offset, i2c_reg, value, mask, data);
offset, reg, val.byte, mask, data);
value = (value & mask) | data;
if (!bios->execute)
continue;
if (bios->execute) {
msg.addr = i2c_address;
msg.flags = 0;
msg.len = 1;
msg.buf = &value;
if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
return 0;
}
val.byte &= mask;
val.byte |= data;
ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
I2C_SMBUS_WRITE, reg,
I2C_SMBUS_BYTE_DATA, &val);
if (ret < 0)
return ret;
}
return len;
@ -1301,12 +1516,11 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
*/
uint8_t i2c_index = bios->data[offset + 1];
uint8_t i2c_address = bios->data[offset + 2];
uint8_t i2c_address = bios->data[offset + 2] >> 1;
uint8_t count = bios->data[offset + 3];
int len = 4 + count * 2;
struct nouveau_i2c_chan *chan;
struct i2c_msg msg;
int i;
int len = 4 + count * 2;
int ret, i;
if (!iexec->execute)
return len;
@ -1317,23 +1531,25 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
chan = init_i2c_device_find(bios->dev, i2c_index);
if (!chan)
return 0;
return -ENODEV;
for (i = 0; i < count; i++) {
uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
uint8_t data = bios->data[offset + 5 + i * 2];
uint8_t reg = bios->data[offset + 4 + i * 2];
union i2c_smbus_data val;
val.byte = bios->data[offset + 5 + i * 2];
BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
offset, i2c_reg, data);
offset, reg, val.byte);
if (bios->execute) {
msg.addr = i2c_address;
msg.flags = 0;
msg.len = 1;
msg.buf = &data;
if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
return 0;
}
if (!bios->execute)
continue;
ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
I2C_SMBUS_WRITE, reg,
I2C_SMBUS_BYTE_DATA, &val);
if (ret < 0)
return ret;
}
return len;
@ -1357,7 +1573,7 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
*/
uint8_t i2c_index = bios->data[offset + 1];
uint8_t i2c_address = bios->data[offset + 2];
uint8_t i2c_address = bios->data[offset + 2] >> 1;
uint8_t count = bios->data[offset + 3];
int len = 4 + count;
struct nouveau_i2c_chan *chan;
@ -1374,7 +1590,7 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
chan = init_i2c_device_find(bios->dev, i2c_index);
if (!chan)
return 0;
return -ENODEV;
for (i = 0; i < count; i++) {
data[i] = bios->data[offset + 4 + i];
@ -1388,7 +1604,7 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
msg.len = count;
msg.buf = data;
if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
return 0;
return -EIO;
}
return len;
@ -1427,7 +1643,7 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
reg = get_tmds_index_reg(bios->dev, mlv);
if (!reg)
return 0;
return -EINVAL;
bios_wr32(bios, reg,
tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
@ -1471,7 +1687,7 @@ init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
reg = get_tmds_index_reg(bios->dev, mlv);
if (!reg)
return 0;
return -EINVAL;
for (i = 0; i < count; i++) {
uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
@ -1946,7 +2162,7 @@ init_configure_mem(struct nvbios *bios, uint16_t offset,
uint32_t reg, data;
if (bios->major_version > 2)
return 0;
return -ENODEV;
bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
@ -2001,7 +2217,7 @@ init_configure_clk(struct nvbios *bios, uint16_t offset,
int clock;
if (bios->major_version > 2)
return 0;
return -ENODEV;
clock = ROM16(bios->data[meminitoffs + 4]) * 10;
setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
@ -2034,7 +2250,7 @@ init_configure_preinit(struct nvbios *bios, uint16_t offset,
uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
if (bios->major_version > 2)
return 0;
return -ENODEV;
bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
@ -2656,7 +2872,7 @@ init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
NV_ERROR(bios->dev,
"0x%04X: Zero block length - has the M table "
"been parsed?\n", offset);
return 0;
return -EINVAL;
}
strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
@ -2840,14 +3056,14 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
if (!bios->display.output) {
NV_ERROR(dev, "INIT_AUXCH: no active output\n");
return 0;
return -EINVAL;
}
auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
if (!auxch) {
NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
bios->display.output->i2c_index);
return 0;
return -ENODEV;
}
if (!iexec->execute)
@ -2860,7 +3076,7 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
if (ret) {
NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
return 0;
return ret;
}
data &= bios->data[offset + 0];
@ -2869,7 +3085,7 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
if (ret) {
NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
return 0;
return ret;
}
}
@ -2899,14 +3115,14 @@ init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
if (!bios->display.output) {
NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
return 0;
return -EINVAL;
}
auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
if (!auxch) {
NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
bios->display.output->i2c_index);
return 0;
return -ENODEV;
}
if (!iexec->execute)
@ -2917,7 +3133,7 @@ init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
if (ret) {
NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
return 0;
return ret;
}
}
@ -2934,6 +3150,9 @@ static struct init_tbl_entry itbl_entry[] = {
{ "INIT_COPY" , 0x37, init_copy },
{ "INIT_NOT" , 0x38, init_not },
{ "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
{ "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
{ "INIT_OP_3B" , 0x3B, init_op_3b },
{ "INIT_OP_3C" , 0x3C, init_op_3c },
{ "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
{ "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
{ "INIT_PLL2" , 0x4B, init_pll2 },
@ -3001,7 +3220,7 @@ parse_init_table(struct nvbios *bios, unsigned int offset,
* is changed back to EXECUTE.
*/
int count = 0, i, res;
int count = 0, i, ret;
uint8_t id;
/*
@ -3016,26 +3235,33 @@ parse_init_table(struct nvbios *bios, unsigned int offset,
for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
;
if (itbl_entry[i].name) {
BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n",
offset, itbl_entry[i].id, itbl_entry[i].name);
/* execute eventual command handler */
res = (*itbl_entry[i].handler)(bios, offset, iexec);
if (!res)
break;
/*
* Add the offset of the current command including all data
* of that command. The offset will then be pointing on the
* next op code.
*/
offset += res;
} else {
if (!itbl_entry[i].name) {
NV_ERROR(bios->dev,
"0x%04X: Init table command not found: "
"0x%02X\n", offset, id);
return -ENOENT;
}
BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
itbl_entry[i].id, itbl_entry[i].name);
/* execute eventual command handler */
ret = (*itbl_entry[i].handler)(bios, offset, iexec);
if (ret < 0) {
NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
"table opcode: %s %d\n", offset,
itbl_entry[i].name, ret);
}
if (ret <= 0)
break;
/*
* Add the offset of the current command including all data
* of that command. The offset will then be pointing on the
* next op code.
*/
offset += ret;
}
if (offset >= bios->length)
@ -4285,31 +4511,32 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims
break;
}
#if 0 /* for easy debugging */
ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
ErrorF("pll.max_log2p: %d\n", pll_lim->max_log2p);
ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
ErrorF("pll.refclk: %d\n", pll_lim->refclk);
#endif
NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
if (pll_lim->vco2.maxfreq) {
NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
}
if (!pll_lim->max_p) {
NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
} else {
NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
}
NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
return 0;
}
@ -4953,79 +5180,6 @@ static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
return 0;
}
static int
read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
{
uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
int recordoffset = 0, rdofs = 1, wrofs = 0;
uint8_t port_type = 0;
if (!i2ctable)
return -EINVAL;
if (dcb_version >= 0x30) {
if (i2ctable[0] != dcb_version) /* necessary? */
NV_WARN(dev,
"DCB I2C table version mismatch (%02X vs %02X)\n",
i2ctable[0], dcb_version);
dcb_i2c_ver = i2ctable[0];
headerlen = i2ctable[1];
if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
i2c_entries = i2ctable[2];
else
NV_WARN(dev,
"DCB I2C table has more entries than indexable "
"(%d entries, max %d)\n", i2ctable[2],
DCB_MAX_NUM_I2C_ENTRIES);
entry_len = i2ctable[3];
/* [4] is i2c_default_indices, read in parse_dcb_table() */
}
/*
* It's your own fault if you call this function on a DCB 1.1 BIOS --
* the test below is for DCB 1.2
*/
if (dcb_version < 0x14) {
recordoffset = 2;
rdofs = 0;
wrofs = 1;
}
if (index == 0xf)
return 0;
if (index >= i2c_entries) {
NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
index, i2ctable[2]);
return -ENOENT;
}
if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
NV_ERROR(dev, "DCB I2C entry invalid\n");
return -EINVAL;
}
if (dcb_i2c_ver >= 0x30) {
port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
/*
* Fixup for chips using same address offset for read and
* write.
*/
if (port_type == 4) /* seen on C51 */
rdofs = wrofs = 1;
if (port_type >= 5) /* G80+ */
rdofs = wrofs = 0;
}
if (dcb_i2c_ver >= 0x40 && port_type != 5 && port_type != 6)
NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
i2c->port_type = port_type;
i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
return 0;
}
static struct dcb_gpio_entry *
new_gpio_entry(struct nvbios *bios)
{

1
drivers/gpu/drm/nouveau/nouveau_bios.h
View File

@ -35,6 +35,7 @@
#define DCB_LOC_ON_CHIP 0
struct dcb_i2c_entry {
uint32_t entry;
uint8_t port_type;
uint8_t read, write;
struct nouveau_i2c_chan *chan;

2
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -160,11 +160,11 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
ttm_bo_type_device, &nvbo->placement, align, 0,
false, NULL, size, nouveau_bo_del_ttm);
nvbo->channel = NULL;
if (ret) {
/* ttm will call nouveau_bo_del_ttm if it fails.. */
return ret;
}
nvbo->channel = NULL;
spin_lock(&dev_priv->ttm.bo_list_lock);
list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);

6
drivers/gpu/drm/nouveau/nouveau_drv.h
View File

@ -1170,6 +1170,12 @@ int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
/* nv50_calc. */
int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
int *N1, int *M1, int *N2, int *M2, int *P);
int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
int clk, int *N, int *fN, int *M, int *P);
#ifndef ioread32_native
#ifdef __BIG_ENDIAN
#define ioread16_native ioread16be

2
drivers/gpu/drm/nouveau/nouveau_encoder.h
View File

@ -48,6 +48,8 @@ struct nouveau_encoder {
union {
struct {
int mc_unknown;
uint32_t unk0;
uint32_t unk1;
int dpcd_version;
int link_nr;
int link_bw;

21
drivers/gpu/drm/nouveau/nouveau_i2c.c
View File

@ -254,16 +254,27 @@ struct nouveau_i2c_chan *
nouveau_i2c_find(struct drm_device *dev, int index)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nvbios *bios = &dev_priv->vbios;
struct dcb_i2c_entry *i2c = &dev_priv->vbios.dcb.i2c[index];
if (index >= DCB_MAX_NUM_I2C_ENTRIES)
return NULL;
if (!bios->dcb.i2c[index].chan) {
if (nouveau_i2c_init(dev, &bios->dcb.i2c[index], index))
return NULL;
if (dev_priv->chipset >= NV_50 && (i2c->entry & 0x00000100)) {
uint32_t reg = 0xe500, val;
if (i2c->port_type == 6) {
reg += i2c->read * 0x50;
val = 0x2002;
} else {
reg += ((i2c->entry & 0x1e00) >> 9) * 0x50;
val = 0xe001;
}
nv_wr32(dev, reg, (nv_rd32(dev, reg) & ~0xf003) | val);
}
return bios->dcb.i2c[index].chan;
if (!i2c->chan && nouveau_i2c_init(dev, i2c, index))
return NULL;
return i2c->chan;
}

1
drivers/gpu/drm/nouveau/nouveau_reg.h
View File

@ -826,6 +826,7 @@
#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000
#define NV50_SOR_DP_UNK118(i,l) (0x0061c118 + (i) * 0x800 + (l) * 0x80)
#define NV50_SOR_DP_UNK120(i,l) (0x0061c120 + (i) * 0x800 + (l) * 0x80)
#define NV50_SOR_DP_UNK128(i,l) (0x0061c128 + (i) * 0x800 + (l) * 0x80)
#define NV50_SOR_DP_UNK130(i,l) (0x0061c130 + (i) * 0x800 + (l) * 0x80)
#define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000)

2
drivers/gpu/drm/nouveau/nv04_fbcon.c
View File

@ -236,7 +236,7 @@ nv04_fbcon_accel_init(struct fb_info *info)
if (ret)
return ret;
ret = nv04_fbcon_grobj_new(dev, dev_priv->card_type >= NV_10 ?
ret = nv04_fbcon_grobj_new(dev, dev_priv->chipset >= 0x11 ?
0x009f : 0x005f, NvImageBlit);
if (ret)
return ret;

566
drivers/gpu/drm/nouveau/nv04_graph.c
View File

@ -532,9 +532,82 @@ nv04_graph_mthd_set_ref(struct nouveau_channel *chan, int grclass,
return 0;
}
static int
nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
/*
* Software methods, why they are needed, and how they all work:
*
* NV04 and NV05 keep most of the state in PGRAPH context itself, but some
* 2d engine settings are kept inside the grobjs themselves. The grobjs are
* 3 words long on both. grobj format on NV04 is:
*
* word 0:
* - bits 0-7: class
* - bit 12: color key active
* - bit 13: clip rect active
* - bit 14: if set, destination surface is swizzled and taken from buffer 5
* [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
* from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
* NV03_CONTEXT_SURFACE_DST].
* - bits 15-17: 2d operation [aka patch config]
* - bit 24: patch valid [enables rendering using this object]
* - bit 25: surf3d valid [for tex_tri and multitex_tri only]
* word 1:
* - bits 0-1: mono format
* - bits 8-13: color format
* - bits 16-31: DMA_NOTIFY instance
* word 2:
* - bits 0-15: DMA_A instance
* - bits 16-31: DMA_B instance
*
* On NV05 it's:
*
* word 0:
* - bits 0-7: class
* - bit 12: color key active
* - bit 13: clip rect active
* - bit 14: if set, destination surface is swizzled and taken from buffer 5
* [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
* from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
* NV03_CONTEXT_SURFACE_DST].
* - bits 15-17: 2d operation [aka patch config]
* - bits 20-22: dither mode
* - bit 24: patch valid [enables rendering using this object]
* - bit 25: surface_dst/surface_color/surf2d/surf3d valid
* - bit 26: surface_src/surface_zeta valid
* - bit 27: pattern valid
* - bit 28: rop valid
* - bit 29: beta1 valid
* - bit 30: beta4 valid
* word 1:
* - bits 0-1: mono format
* - bits 8-13: color format
* - bits 16-31: DMA_NOTIFY instance
* word 2:
* - bits 0-15: DMA_A instance
* - bits 16-31: DMA_B instance
*
* NV05 will set/unset the relevant valid bits when you poke the relevant
* object-binding methods with object of the proper type, or with the NULL
* type. It'll only allow rendering using the grobj if all needed objects
* are bound. The needed set of objects depends on selected operation: for
* example rop object is needed by ROP_AND, but not by SRCCOPY_AND.
*
* NV04 doesn't have these methods implemented at all, and doesn't have the
* relevant bits in grobj. Instead, it'll allow rendering whenever bit 24
* is set. So we have to emulate them in software, internally keeping the
* same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04,
* but the last word isn't actually used for anything, we abuse it for this
* purpose.
*
* Actually, NV05 can optionally check bit 24 too, but we disable this since
* there's no use for it.
*
* For unknown reasons, NV04 implements surf3d binding in hardware as an
* exception. Also for unknown reasons, NV04 doesn't implement the clipping
* methods on the surf3d object, so we have to emulate them too.
*/
static void
nv04_graph_set_ctx1(struct nouveau_channel *chan, uint32_t mask, uint32_t value)
{
struct drm_device *dev = chan->dev;
uint32_t instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
@ -542,42 +615,509 @@ nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
uint32_t tmp;
tmp = nv_ri32(dev, instance);
tmp &= ~0x00038000;
tmp |= ((data & 7) << 15);
tmp &= ~mask;
tmp |= value;
nv_wi32(dev, instance, tmp);
nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
}
static void
nv04_graph_set_ctx_val(struct nouveau_channel *chan, uint32_t mask, uint32_t value)
{
struct drm_device *dev = chan->dev;
uint32_t instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
uint32_t tmp, ctx1;
int class, op, valid = 1;
ctx1 = nv_ri32(dev, instance);
class = ctx1 & 0xff;
op = (ctx1 >> 15) & 7;
tmp = nv_ri32(dev, instance + 0xc);
tmp &= ~mask;
tmp |= value;
nv_wi32(dev, instance + 0xc, tmp);
/* check for valid surf2d/surf_dst/surf_color */
if (!(tmp & 0x02000000))
valid = 0;
/* check for valid surf_src/surf_zeta */
if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000))
valid = 0;
switch (op) {
/* SRCCOPY_AND, SRCCOPY: no extra objects required */
case 0:
case 3:
break;
/* ROP_AND: requires pattern and rop */
case 1:
if (!(tmp & 0x18000000))
valid = 0;
break;
/* BLEND_AND: requires beta1 */
case 2:
if (!(tmp & 0x20000000))
valid = 0;
break;
/* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */
case 4:
case 5:
if (!(tmp & 0x40000000))
valid = 0;
break;
}
nv04_graph_set_ctx1(chan, 0x01000000, valid << 24);
}
static int
nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
if (data > 5)
return 1;
/* Old versions of the objects only accept first three operations. */
if (data > 2 && grclass < 0x40)
return 1;
nv04_graph_set_ctx1(chan, 0x00038000, data << 15);
/* changing operation changes set of objects needed for validation */
nv04_graph_set_ctx_val(chan, 0, 0);
return 0;
}
static int
nv04_graph_mthd_surf3d_clip_h(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
uint32_t min = data & 0xffff, max;
uint32_t w = data >> 16;
if (min & 0x8000)
/* too large */
return 1;
if (w & 0x8000)
/* yes, it accepts negative for some reason. */
w |= 0xffff0000;
max = min + w;
max &= 0x3ffff;
nv_wr32(chan->dev, 0x40053c, min);
nv_wr32(chan->dev, 0x400544, max);
return 0;
}
static int
nv04_graph_mthd_surf3d_clip_v(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
uint32_t min = data & 0xffff, max;
uint32_t w = data >> 16;
if (min & 0x8000)
/* too large */
return 1;
if (w & 0x8000)
/* yes, it accepts negative for some reason. */
w |= 0xffff0000;
max = min + w;
max &= 0x3ffff;
nv_wr32(chan->dev, 0x400540, min);
nv_wr32(chan->dev, 0x400548, max);
return 0;
}
static int
nv04_graph_mthd_bind_surf2d(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx1(chan, 0x00004000, 0);
nv04_graph_set_ctx_val(chan, 0x02000000, 0);
return 0;
case 0x42:
nv04_graph_set_ctx1(chan, 0x00004000, 0);
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx1(chan, 0x00004000, 0);
nv04_graph_set_ctx_val(chan, 0x02000000, 0);
return 0;
case 0x42:
nv04_graph_set_ctx1(chan, 0x00004000, 0);
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
return 0;
case 0x52:
nv04_graph_set_ctx1(chan, 0x00004000, 0x00004000);
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_nv01_patt(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x08000000, 0);
return 0;
case 0x18:
nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_nv04_patt(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x08000000, 0);
return 0;
case 0x44:
nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_rop(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x10000000, 0);
return 0;
case 0x43:
nv04_graph_set_ctx_val(chan, 0x10000000, 0x10000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_beta1(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x20000000, 0);
return 0;
case 0x12:
nv04_graph_set_ctx_val(chan, 0x20000000, 0x20000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_beta4(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x40000000, 0);
return 0;
case 0x72:
nv04_graph_set_ctx_val(chan, 0x40000000, 0x40000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_surf_dst(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x02000000, 0);
return 0;
case 0x58:
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_surf_src(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x04000000, 0);
return 0;
case 0x59:
nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_surf_color(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x02000000, 0);
return 0;
case 0x5a:
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_surf_zeta(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx_val(chan, 0x04000000, 0);
return 0;
case 0x5b:
nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_clip(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx1(chan, 0x2000, 0);
return 0;
case 0x19:
nv04_graph_set_ctx1(chan, 0x2000, 0x2000);
return 0;
}
return 1;
}
static int
nv04_graph_mthd_bind_chroma(struct nouveau_channel *chan, int grclass,
int mthd, uint32_t data)
{
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
case 0x30:
nv04_graph_set_ctx1(chan, 0x1000, 0);
return 0;
/* Yes, for some reason even the old versions of objects
* accept 0x57 and not 0x17. Consistency be damned.
*/
case 0x57:
nv04_graph_set_ctx1(chan, 0x1000, 0x1000);
return 0;
}
return 1;
}
static struct nouveau_pgraph_object_method nv04_graph_mthds_sw[] = {
{ 0x0150, nv04_graph_mthd_set_ref },
{}
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_set_operation[] = {
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_gdirect[] = {
{ 0x0184, nv04_graph_mthd_bind_nv01_patt },
{ 0x0188, nv04_graph_mthd_bind_rop },
{ 0x018c, nv04_graph_mthd_bind_beta1 },
{ 0x0190, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_gdirect[] = {
{ 0x0188, nv04_graph_mthd_bind_nv04_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv01_imageblit[] = {
{ 0x0184, nv04_graph_mthd_bind_chroma },
{ 0x0188, nv04_graph_mthd_bind_clip },
{ 0x018c, nv04_graph_mthd_bind_nv01_patt },
{ 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, nv04_graph_mthd_bind_surf_dst },
{ 0x019c, nv04_graph_mthd_bind_surf_src },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_imageblit_ifc[] = {
{ 0x0184, nv04_graph_mthd_bind_chroma },
{ 0x0188, nv04_graph_mthd_bind_clip },
{ 0x018c, nv04_graph_mthd_bind_nv04_patt },
{ 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, nv04_graph_mthd_bind_beta4 },
{ 0x019c, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_iifc[] = {
{ 0x0188, nv04_graph_mthd_bind_chroma },
{ 0x018c, nv04_graph_mthd_bind_clip },
{ 0x0190, nv04_graph_mthd_bind_nv04_patt },
{ 0x0194, nv04_graph_mthd_bind_rop },
{ 0x0198, nv04_graph_mthd_bind_beta1 },
{ 0x019c, nv04_graph_mthd_bind_beta4 },
{ 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf },
{ 0x03e4, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv01_ifc[] = {
{ 0x0184, nv04_graph_mthd_bind_chroma },
{ 0x0188, nv04_graph_mthd_bind_clip },
{ 0x018c, nv04_graph_mthd_bind_nv01_patt },
{ 0x0190, nv04_graph_mthd_bind_rop },
{ 0x0194, nv04_graph_mthd_bind_beta1 },
{ 0x0198, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_sifc[] = {
{ 0x0184, nv04_graph_mthd_bind_chroma },
{ 0x0188, nv04_graph_mthd_bind_nv01_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_sifc[] = {
{ 0x0184, nv04_graph_mthd_bind_chroma },
{ 0x0188, nv04_graph_mthd_bind_nv04_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_sifm[] = {
{ 0x0188, nv04_graph_mthd_bind_nv01_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x0304, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_sifm[] = {
{ 0x0188, nv04_graph_mthd_bind_nv04_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, nv04_graph_mthd_bind_surf2d_swzsurf },
{ 0x0304, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv01_shape[] = {
{ 0x0184, nv04_graph_mthd_bind_clip },
{ 0x0188, nv04_graph_mthd_bind_nv01_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_surf_dst },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_shape[] = {
{ 0x0184, nv04_graph_mthd_bind_clip },
{ 0x0188, nv04_graph_mthd_bind_nv04_patt },
{ 0x018c, nv04_graph_mthd_bind_rop },
{ 0x0190, nv04_graph_mthd_bind_beta1 },
{ 0x0194, nv04_graph_mthd_bind_beta4 },
{ 0x0198, nv04_graph_mthd_bind_surf2d },
{ 0x02fc, nv04_graph_mthd_set_operation },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_tex_tri[] = {
{ 0x0188, nv04_graph_mthd_bind_clip },
{ 0x018c, nv04_graph_mthd_bind_surf_color },
{ 0x0190, nv04_graph_mthd_bind_surf_zeta },
{},
};
static struct nouveau_pgraph_object_method nv04_graph_mthds_surf3d[] = {
{ 0x02f8, nv04_graph_mthd_surf3d_clip_h },
{ 0x02fc, nv04_graph_mthd_surf3d_clip_v },
{},
};
struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
{ 0x0039, false, NULL },
{ 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */
{ 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */
{ 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */
{ 0x0077, false, nv04_graph_mthds_set_operation }, /* sifm */
{ 0x0038, false, NULL }, /* dvd subpicture */
{ 0x0039, false, NULL }, /* m2mf */
{ 0x004b, false, nv04_graph_mthds_nv03_gdirect }, /* nv03 gdirect */
{ 0x004a, false, nv04_graph_mthds_nv04_gdirect }, /* nv04 gdirect */
{ 0x001f, false, nv04_graph_mthds_nv01_imageblit }, /* nv01 imageblit */
{ 0x005f, false, nv04_graph_mthds_nv04_imageblit_ifc }, /* nv04 imageblit */
{ 0x0060, false, nv04_graph_mthds_nv04_iifc }, /* nv04 iifc */
{ 0x0064, false, NULL }, /* nv05 iifc */
{ 0x0021, false, nv04_graph_mthds_nv01_ifc }, /* nv01 ifc */
{ 0x0061, false, nv04_graph_mthds_nv04_imageblit_ifc }, /* nv04 ifc */
{ 0x0065, false, NULL }, /* nv05 ifc */
{ 0x0036, false, nv04_graph_mthds_nv03_sifc }, /* nv03 sifc */
{ 0x0076, false, nv04_graph_mthds_nv04_sifc }, /* nv04 sifc */
{ 0x0066, false, NULL }, /* nv05 sifc */
{ 0x0037, false, nv04_graph_mthds_nv03_sifm }, /* nv03 sifm */
{ 0x0077, false, nv04_graph_mthds_nv04_sifm }, /* nv04 sifm */
{ 0x0030, false, NULL }, /* null */
{ 0x0042, false, NULL }, /* surf2d */
{ 0x0043, false, NULL }, /* rop */
{ 0x0012, false, NULL }, /* beta1 */
{ 0x0072, false, NULL }, /* beta4 */
{ 0x0019, false, NULL }, /* cliprect */
{ 0x0044, false, NULL }, /* pattern */
{ 0x0018, false, NULL }, /* nv01 pattern */
{ 0x0044, false, NULL }, /* nv04 pattern */
{ 0x0052, false, NULL }, /* swzsurf */
{ 0x0053, false, NULL }, /* surf3d */
{ 0x0053, false, nv04_graph_mthds_surf3d }, /* surf3d */
{ 0x0048, false, nv04_graph_mthds_nv03_tex_tri }, /* nv03 tex_tri */
{ 0x0054, false, NULL }, /* tex_tri */
{ 0x0055, false, NULL }, /* multitex_tri */
{ 0x0017, false, NULL }, /* nv01 chroma */
{ 0x0057, false, NULL }, /* nv04 chroma */
{ 0x0058, false, NULL }, /* surf_dst */
{ 0x0059, false, NULL }, /* surf_src */
{ 0x005a, false, NULL }, /* surf_color */
{ 0x005b, false, NULL }, /* surf_zeta */
{ 0x001c, false, nv04_graph_mthds_nv01_shape }, /* nv01 line */
{ 0x005c, false, nv04_graph_mthds_nv04_shape }, /* nv04 line */
{ 0x001d, false, nv04_graph_mthds_nv01_shape }, /* nv01 tri */
{ 0x005d, false, nv04_graph_mthds_nv04_shape }, /* nv04 tri */
{ 0x001e, false, nv04_graph_mthds_nv01_shape }, /* nv01 rect */
{ 0x005e, false, nv04_graph_mthds_nv04_shape }, /* nv04 rect */
{ 0x506e, true, nv04_graph_mthds_sw },
{}
};

5
drivers/gpu/drm/nouveau/nv40_grctx.c
View File

@ -115,11 +115,6 @@
/* TODO:
* - get vs count from 0x1540
* - document unimplemented bits compared to nvidia
* - nsource handling
* - R0 & 0x0200 handling
* - single-vs handling
* - 400314 bit 0
*/
static int

87
drivers/gpu/drm/nouveau/nv50_calc.c Normal file
View File

@ -0,0 +1,87 @@
/*
* Copyright 2010 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "drmP.h"
#include "drm_fixed.h"
#include "nouveau_drv.h"
#include "nouveau_hw.h"
int
nv50_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk,
int *N1, int *M1, int *N2, int *M2, int *P)
{
struct nouveau_pll_vals pll_vals;
int ret;
ret = nouveau_calc_pll_mnp(dev, pll, clk, &pll_vals);
if (ret <= 0)
return ret;
*N1 = pll_vals.N1;
*M1 = pll_vals.M1;
*N2 = pll_vals.N2;
*M2 = pll_vals.M2;
*P = pll_vals.log2P;
return ret;
}
int
nv50_calc_pll2(struct drm_device *dev, struct pll_lims *pll, int clk,
int *N, int *fN, int *M, int *P)
{
fixed20_12 fb_div, a, b;
*P = pll->vco1.maxfreq / clk;
if (*P > pll->max_p)
*P = pll->max_p;
if (*P < pll->min_p)
*P = pll->min_p;
/* *M = ceil(refclk / pll->vco.max_inputfreq); */
a.full = dfixed_const(pll->refclk);
b.full = dfixed_const(pll->vco1.max_inputfreq);
a.full = dfixed_div(a, b);
a.full = dfixed_ceil(a);
*M = dfixed_trunc(a);
/* fb_div = (vco * *M) / refclk; */
fb_div.full = dfixed_const(clk * *P);
fb_div.full = dfixed_mul(fb_div, a);
a.full = dfixed_const(pll->refclk);
fb_div.full = dfixed_div(fb_div, a);
/* *N = floor(fb_div); */
a.full = dfixed_floor(fb_div);
*N = dfixed_trunc(fb_div);
/* *fN = (fmod(fb_div, 1.0) * 8192) - 4096; */
b.full = dfixed_const(8192);
a.full = dfixed_mul(a, b);
fb_div.full = dfixed_mul(fb_div, b);
fb_div.full = fb_div.full - a.full;
*fN = dfixed_trunc(fb_div) - 4096;
*fN &= 0xffff;
return clk;
}

46
drivers/gpu/drm/nouveau/nv50_crtc.c
View File

@ -264,32 +264,40 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
int
nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
{
uint32_t pll_reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
struct nouveau_pll_vals pll;
struct pll_lims limits;
uint32_t reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
struct pll_lims pll;
uint32_t reg1, reg2;
int ret;
int ret, N1, M1, N2, M2, P;
ret = get_pll_limits(dev, pll_reg, &limits);
ret = get_pll_limits(dev, reg, &pll);
if (ret)
return ret;
ret = nouveau_calc_pll_mnp(dev, &limits, pclk, &pll);
if (ret <= 0)
return ret;
if (pll.vco2.maxfreq) {
ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
if (ret <= 0)
return 0;
if (limits.vco2.maxfreq) {
reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00;
reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00;
nv_wr32(dev, pll_reg, 0x10000611);
nv_wr32(dev, pll_reg + 4, reg1 | (pll.M1 << 16) | pll.N1);
nv_wr32(dev, pll_reg + 8,
reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2);
NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
pclk, ret, N1, M1, N2, M2, P);
reg1 = nv_rd32(dev, reg + 4) & 0xff00ff00;
reg2 = nv_rd32(dev, reg + 8) & 0x8000ff00;
nv_wr32(dev, reg, 0x10000611);
nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1);
nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
} else {
reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000;
nv_wr32(dev, pll_reg, 0x50000610);
nv_wr32(dev, pll_reg + 4, reg1 |
(pll.log2P << 16) | (pll.M1 << 8) | pll.N1);
ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
if (ret <= 0)
return 0;
NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
pclk, ret, N1, N2, M1, P);
reg1 = nv_rd32(dev, reg + 4) & 0xffc00000;
nv_wr32(dev, reg, 0x50000610);
nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
nv_wr32(dev, reg + 8, N2);
}
return 0;

33
drivers/gpu/drm/nouveau/nv50_display.c
View File

@ -783,6 +783,37 @@ ack:
nv_wr32(dev, 0x610030, 0x80000000);
}
static void
nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
{
int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
struct drm_encoder *encoder;
uint32_t tmp, unk0 = 0, unk1 = 0;
if (dcb->type != OUTPUT_DP)
return;
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
if (nv_encoder->dcb == dcb) {
unk0 = nv_encoder->dp.unk0;
unk1 = nv_encoder->dp.unk1;
break;
}
}
if (unk0 || unk1) {
tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
tmp &= 0xfffffe03;
nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
tmp &= 0xfef080c0;
nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
}
}
static void
nv50_display_unk20_handler(struct drm_device *dev)
{
@ -806,6 +837,8 @@ nv50_display_unk20_handler(struct drm_device *dev)
nouveau_bios_run_display_table(dev, dcbent, script, pclk);
nv50_display_unk20_dp_hack(dev, dcbent);
tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head));
tmp &= ~0x000000f;
nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head), tmp);

15
drivers/gpu/drm/nouveau/nv50_sor.c
View File

@ -321,18 +321,23 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
encoder->possible_clones = 0;
if (nv_encoder->dcb->type == OUTPUT_DP) {
uint32_t mc, or = nv_encoder->or;
int or = nv_encoder->or, link = !(entry->dpconf.sor.link & 1);
uint32_t tmp;
if (dev_priv->chipset < 0x90 ||
dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or));
tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or));
else
mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or));
tmp = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or));
switch ((mc & 0x00000f00) >> 8) {
switch ((tmp & 0x00000f00) >> 8) {
case 8:
case 9:
nv_encoder->dp.mc_unknown = (mc & 0x000f0000) >> 16;
nv_encoder->dp.mc_unknown = (tmp & 0x000f0000) >> 16;
tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
nv_encoder->dp.unk0 = tmp & 0x000001fc;
tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
nv_encoder->dp.unk1 = tmp & 0x010f7f3f;
break;
default:
break;