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powerpc/pseries: Fix endian issues in pseries iommu code
Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
parent
3e7cec6b17
commit
df015604cf
@ -52,7 +52,7 @@
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static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
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u64 *startp, u64 *endp)
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__be64 *startp, __be64 *endp)
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{
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u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
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unsigned long start, end, inc;
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@ -86,7 +86,7 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
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struct dma_attrs *attrs)
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{
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u64 proto_tce;
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u64 *tcep, *tces;
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__be64 *tcep, *tces;
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u64 rpn;
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proto_tce = TCE_PCI_READ; // Read allowed
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@ -94,12 +94,12 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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tces = tcep = ((u64 *)tbl->it_base) + index;
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tces = tcep = ((__be64 *)tbl->it_base) + index;
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while (npages--) {
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/* can't move this out since we might cross MEMBLOCK boundary */
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rpn = __pa(uaddr) >> TCE_SHIFT;
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*tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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*tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
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uaddr += TCE_PAGE_SIZE;
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tcep++;
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@ -113,9 +113,9 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
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static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
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{
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u64 *tcep, *tces;
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__be64 *tcep, *tces;
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tces = tcep = ((u64 *)tbl->it_base) + index;
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tces = tcep = ((__be64 *)tbl->it_base) + index;
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while (npages--)
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*(tcep++) = 0;
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@ -126,11 +126,11 @@ static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
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static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
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{
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u64 *tcep;
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__be64 *tcep;
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tcep = ((u64 *)tbl->it_base) + index;
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tcep = ((__be64 *)tbl->it_base) + index;
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return *tcep;
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return be64_to_cpu(*tcep);
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}
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static void tce_free_pSeriesLP(struct iommu_table*, long, long);
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@ -177,7 +177,7 @@ static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
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return ret;
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}
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static DEFINE_PER_CPU(u64 *, tce_page);
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static DEFINE_PER_CPU(__be64 *, tce_page);
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static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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long npages, unsigned long uaddr,
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@ -186,7 +186,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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{
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u64 rc = 0;
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u64 proto_tce;
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u64 *tcep;
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__be64 *tcep;
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u64 rpn;
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long l, limit;
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long tcenum_start = tcenum, npages_start = npages;
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@ -206,7 +206,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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* from iommu_alloc{,_sg}()
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*/
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if (!tcep) {
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tcep = (u64 *)__get_free_page(GFP_ATOMIC);
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tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
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/* If allocation fails, fall back to the loop implementation */
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if (!tcep) {
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local_irq_restore(flags);
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@ -230,7 +230,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
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for (l = 0; l < limit; l++) {
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tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
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rpn++;
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}
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@ -329,16 +329,16 @@ struct direct_window {
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/* Dynamic DMA Window support */
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struct ddw_query_response {
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u32 windows_available;
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u32 largest_available_block;
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u32 page_size;
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u32 migration_capable;
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__be32 windows_available;
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__be32 largest_available_block;
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__be32 page_size;
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__be32 migration_capable;
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};
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struct ddw_create_response {
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u32 liobn;
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u32 addr_hi;
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u32 addr_lo;
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__be32 liobn;
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__be32 addr_hi;
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__be32 addr_lo;
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};
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static LIST_HEAD(direct_window_list);
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@ -392,7 +392,8 @@ static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
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unsigned long num_pfn, const void *arg)
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{
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const struct dynamic_dma_window_prop *maprange = arg;
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u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn;
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u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
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__be64 *tcep;
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u32 tce_shift;
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u64 rc = 0;
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long l, limit;
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@ -401,7 +402,7 @@ static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
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tcep = __get_cpu_var(tce_page);
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if (!tcep) {
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tcep = (u64 *)__get_free_page(GFP_ATOMIC);
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tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
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if (!tcep) {
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local_irq_enable();
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return -ENOMEM;
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@ -435,7 +436,7 @@ static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
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dma_offset = next + be64_to_cpu(maprange->dma_base);
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for (l = 0; l < limit; l++) {
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tcep[l] = proto_tce | next;
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tcep[l] = cpu_to_be64(proto_tce | next);
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next += tce_size;
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}
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@ -780,7 +781,7 @@ static u64 find_existing_ddw(struct device_node *pdn)
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list_for_each_entry(window, &direct_window_list, list) {
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if (window->device == pdn) {
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direct64 = window->prop;
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dma_addr = direct64->dma_base;
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dma_addr = be64_to_cpu(direct64->dma_base);
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break;
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}
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}
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@ -1045,11 +1046,11 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
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dev_dbg(&dev->dev, "no free dynamic windows");
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goto out_restore_window;
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}
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if (query.page_size & 4) {
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if (be32_to_cpu(query.page_size) & 4) {
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page_shift = 24; /* 16MB */
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} else if (query.page_size & 2) {
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} else if (be32_to_cpu(query.page_size) & 2) {
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page_shift = 16; /* 64kB */
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} else if (query.page_size & 1) {
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} else if (be32_to_cpu(query.page_size) & 1) {
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page_shift = 12; /* 4kB */
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} else {
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dev_dbg(&dev->dev, "no supported direct page size in mask %x",
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@ -1059,7 +1060,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
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/* verify the window * number of ptes will map the partition */
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/* check largest block * page size > max memory hotplug addr */
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max_addr = memory_hotplug_max();
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if (query.largest_available_block < (max_addr >> page_shift)) {
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if (be32_to_cpu(query.largest_available_block) < (max_addr >> page_shift)) {
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dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
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"%llu-sized pages\n", max_addr, query.largest_available_block,
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1ULL << page_shift);
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@ -1085,7 +1086,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
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if (ret != 0)
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goto out_free_prop;
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ddwprop->liobn = cpu_to_be32(create.liobn);
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ddwprop->liobn = create.liobn;
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ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2));
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ddwprop->tce_shift = cpu_to_be32(page_shift);
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ddwprop->window_shift = cpu_to_be32(len);
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