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arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for per-variant OPPs
Rename the Rockchip RK3588 SoC dtsi files and, consequently, adjust their contents appropriately, to prepare them for the ability to specify different CPU and GPU OPPs for each of the supported RK3588 SoC variants. As already discussed, [1][2][3][4] some of the RK3588 SoC variants require different OPPs, and it makes more sense to have the OPPs already defined when a board dts(i) file includes one of the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi or rk3588s.dtsi), rather than requiring the board dts(i) file to also include a separate rk3588*-opp.dtsi file. The choice of the SoC variant is already made by the inclusion of the SoC dtsi file into the board dts(i) file, and it doesn't make much sense to, effectively, allow the board dts(i) file to include and use an incompatible set of OPPs for the already selected RK3588 SoC variant. The new naming scheme for the RK3588 SoC dtsi files uses "-base" and "-extra" suffixes to denote the DT data shared between all RK5588 SoC variants, and the DT data shared between the unrestricted SoC variants, respectively. For example, the DT data for the RK3588 includes both rk3588-base.dtsi and rk3588-extra.dtsi, because it's an unrestricted SoC variant, while the DT data for the RK3588S variant includes rk3588-base.dtsi only, because it's a restricted SoC variant, feature- and interface-wise. This achieves a more logical naming of the RK3588 SoC dtsi files, which reflects the way DT data for the SoC variants is built by "stacking" the SoC variant features made available through the "-base" and "-extra" SoC dtsi files. Additionally, the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi and rk3588s.dtsi) are no longer parents to any other SoC variant dtsi files, which should help with making the new "stacking" approach cleaner and easier to follow. The RK3588 pinctrl dtsi files are also renamed in the same way, for the sake of consistency. This also keeps the "-base" and "-extra" groups of the dtsi files together when looked at in a directory listing, which is helpful. The per-SoC-variant OPPs should go directly into the SoC dtsi files, if no more than one SoC variant uses those OPPs, or be put into a separate "-opp" dtsi file that's shared between and included from two or more SoC variant dtsi files. An example for the former is the non-shared OPP data that should go directly into the RK3588J SoC variant dtsi file (i.e. rk3588j.dtsi), and an example for the latter is the shared OPP data that should be put into rk3588-opp.dtsi and be included from the RK3588 and RK3588S SoC variant dtsi files (i.e. rk3588.dtsi and rk3588s.dtsi, respectively). Consequently, if the OPPs for the RK3588 and RK3588S SoC variants are ever made different, the shared rk3588-opp.dtsi file should be deleted and the new OPPs should be put directly into rk3588.dtsi and rk3588s.dtsi. [4] No functional changes are introduced, which was validated by decompiling and comparing all affected dtb files before and after these changes. As a side note, due to the nature of introduced changes, this commit is best viewed using the --break-rewrites option for git-log(1). [1] https://lore.kernel.org/linux-rockchip/646a33e0-5c1b-471c-8183-2c0df40ea51a@cherry.de/ [2] https://lore.kernel.org/linux-rockchip/CABjd4Yxi=+3gkNnH3BysUzzYsji-=-yROtzEc8jM_g0roKB0-w@mail.gmail.com/ [3] https://lore.kernel.org/linux-rockchip/035a274be262528012173d463e25b55f@manjaro.org/ [4] https://lore.kernel.org/linux-rockchip/673dcf47596e7bc8ba065034e339bb1bbf9cdcb0.1716948159.git.dsimic@manjaro.org/T/#u Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/9ffedc0e2ca7f167d9d795b2a8f43cb9f56a653b.1717923308.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Dragan Simic
Heiko Stuebner
parent
e23819cf27
commit
def88eb4d8
2670
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
Normal file
2670
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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File diff suppressed because it is too large
Load Diff
413
arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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413
arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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@ -0,0 +1,413 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include "rk3588-base.dtsi"
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#include "rk3588-extra-pinctrl.dtsi"
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/ {
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usb_host1_xhci: usb@fc400000 {
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compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
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reg = <0x0 0xfc400000 0x0 0x400000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
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<&cru ACLK_USB3OTG1>;
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clock-names = "ref_clk", "suspend_clk", "bus_clk";
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dr_mode = "otg";
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phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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power-domains = <&power RK3588_PD_USB>;
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resets = <&cru SRST_A_USB3OTG1>;
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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status = "disabled";
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};
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pcie30_phy_grf: syscon@fd5b8000 {
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compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
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reg = <0x0 0xfd5b8000 0x0 0x10000>;
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};
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pipe_phy1_grf: syscon@fd5c0000 {
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compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
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reg = <0x0 0xfd5c0000 0x0 0x100>;
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};
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usbdpphy1_grf: syscon@fd5cc000 {
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compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
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reg = <0x0 0xfd5cc000 0x0 0x4000>;
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};
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usb2phy1_grf: syscon@fd5d4000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
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reg = <0x0 0xfd5d4000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy1: usb2phy@4000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0x4000 0x10>;
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#clock-cells = <0>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy1";
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interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
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resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
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reset-names = "phy", "apb";
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status = "disabled";
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u2phy1_otg: otg-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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i2s8_8ch: i2s@fddc8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc8000 0x0 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 22>;
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dma-names = "tx";
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power-domains = <&power RK3588_PD_VO0>;
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resets = <&cru SRST_M_I2S8_8CH_TX>;
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reset-names = "tx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s6_8ch: i2s@fddf4000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf4000 0x0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 4>;
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dma-names = "tx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S6_8CH_TX>;
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reset-names = "tx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s7_8ch: i2s@fddf8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf8000 0x0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 21>;
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dma-names = "rx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S7_8CH_RX>;
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reset-names = "rx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s10_8ch: i2s@fde00000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfde00000 0x0 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 24>;
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dma-names = "rx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S10_8CH_RX>;
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reset-names = "rx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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pcie3x4: pcie@fe150000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0x0f>;
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clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
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<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
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<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
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<0 0 0 2 &pcie3x4_intc 1>,
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<0 0 0 3 &pcie3x4_intc 2>,
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<0 0 0 4 &pcie3x4_intc 3>;
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linux,pci-domain = <0>;
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max-link-speed = <3>;
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msi-map = <0x0000 &its1 0x0000 0x1000>;
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num-lanes = <4>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
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reg = <0xa 0x40000000 0x0 0x00400000>,
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<0x0 0xfe150000 0x0 0x00010000>,
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<0x0 0xf0000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
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reset-names = "pwr", "pipe";
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status = "disabled";
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pcie3x4_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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pcie3x2: pcie@fe160000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x10 0x1f>;
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clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
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<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
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<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
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<0 0 0 2 &pcie3x2_intc 1>,
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<0 0 0 3 &pcie3x2_intc 2>,
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<0 0 0 4 &pcie3x2_intc 3>;
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linux,pci-domain = <1>;
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max-link-speed = <3>;
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msi-map = <0x1000 &its1 0x1000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
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reg = <0xa 0x40400000 0x0 0x00400000>,
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<0x0 0xfe160000 0x0 0x00010000>,
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<0x0 0xf1000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
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reset-names = "pwr", "pipe";
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status = "disabled";
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pcie3x2_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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pcie2x1l0: pcie@fe170000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
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<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
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<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
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<0 0 0 2 &pcie2x1l0_intc 1>,
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<0 0 0 3 &pcie2x1l0_intc 2>,
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<0 0 0 4 &pcie2x1l0_intc 3>;
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linux,pci-domain = <2>;
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max-link-speed = <2>;
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msi-map = <0x2000 &its0 0x2000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy1_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
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reg = <0xa 0x40800000 0x0 0x00400000>,
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<0x0 0xfe170000 0x0 0x00010000>,
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<0x0 0xf2000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
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reset-names = "pwr", "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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pcie2x1l0_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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gmac0: ethernet@fe1b0000 {
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compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe1b0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
|
||||
<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
|
||||
<&cru CLK_GMAC0_PTP_REF>;
|
||||
clock-names = "stmmaceth", "clk_mac_ref",
|
||||
"pclk_mac", "aclk_mac",
|
||||
"ptp_ref";
|
||||
power-domains = <&power RK3588_PD_GMAC>;
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,php-grf = <&php_grf>;
|
||||
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
snps,mixed-burst;
|
||||
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
snps,tso;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
};
|
||||
|
||||
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,blen = <0 0 0 0 16 8 4>;
|
||||
snps,wr_osr_lmt = <4>;
|
||||
snps,rd_osr_lmt = <8>;
|
||||
};
|
||||
|
||||
gmac0_mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <2>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
};
|
||||
|
||||
gmac0_mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <2>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
};
|
||||
};
|
||||
|
||||
sata1: sata@fe220000 {
|
||||
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfe220000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
|
||||
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
|
||||
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
|
||||
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
||||
ports-implemented = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
sata-port@0 {
|
||||
reg = <0>;
|
||||
hba-port-cap = <HBA_PORT_FBSCP>;
|
||||
phys = <&combphy1_ps PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
snps,rx-ts-max = <32>;
|
||||
snps,tx-ts-max = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
usbdp_phy1: phy@fed90000 {
|
||||
compatible = "rockchip,rk3588-usbdp-phy";
|
||||
reg = <0x0 0xfed90000 0x0 0x10000>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
<&cru CLK_USBDP_PHY1_IMMORTAL>,
|
||||
<&cru PCLK_USBDPPHY1>,
|
||||
<&u2phy1>;
|
||||
clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
||||
<&cru SRST_P_USBDPPHY1>;
|
||||
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
rockchip,u2phy-grf = <&usb2phy1_grf>;
|
||||
rockchip,usb-grf = <&usb_grf>;
|
||||
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
combphy1_ps: phy@fee10000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee10000 0x0 0x100>;
|
||||
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
|
||||
<&cru PCLK_PHP_ROOT>;
|
||||
clock-names = "ref", "apb", "pipe";
|
||||
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
#phy-cells = <1>;
|
||||
resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
|
||||
reset-names = "phy", "apb";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie30phy: phy@fee80000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy";
|
||||
reg = <0x0 0xfee80000 0x0 0x20000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
|
||||
clock-names = "pclk";
|
||||
resets = <&cru SRST_PCIE30_PHY>;
|
||||
reset-names = "phy";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,phy-grf = <&pcie30_phy_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -1,413 +1,7 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3588s.dtsi"
|
||||
#include "rk3588-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
usb_host1_xhci: usb@fc400000 {
|
||||
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xfc400000 0x0 0x400000>;
|
||||
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
|
||||
<&cru ACLK_USB3OTG1>;
|
||||
clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
||||
dr_mode = "otg";
|
||||
phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
phy_type = "utmi_wide";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
resets = <&cru SRST_A_USB3OTG1>;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u2-freeclk-exists-quirk;
|
||||
snps,dis-del-phy-power-chg-quirk;
|
||||
snps,dis-tx-ipgap-linecheck-quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie30_phy_grf: syscon@fd5b8000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pipe_phy1_grf: syscon@fd5c0000 {
|
||||
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5c0000 0x0 0x100>;
|
||||
};
|
||||
|
||||
usbdpphy1_grf: syscon@fd5cc000 {
|
||||
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
reg = <0x0 0xfd5cc000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usb2phy1_grf: syscon@fd5d4000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d4000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy1: usb2phy@4000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x4000 0x10>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy1";
|
||||
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy1_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2s8_8ch: i2s@fddc8000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc8000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 22>;
|
||||
dma-names = "tx";
|
||||
power-domains = <&power RK3588_PD_VO0>;
|
||||
resets = <&cru SRST_M_I2S8_8CH_TX>;
|
||||
reset-names = "tx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s6_8ch: i2s@fddf4000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddf4000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 4>;
|
||||
dma-names = "tx";
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_M_I2S6_8CH_TX>;
|
||||
reset-names = "tx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s7_8ch: i2s@fddf8000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddf8000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 21>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_M_I2S7_8CH_RX>;
|
||||
reset-names = "rx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s10_8ch: i2s@fde00000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfde00000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 24>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_M_I2S10_8CH_RX>;
|
||||
reset-names = "rx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie3x4: pcie@fe150000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0x0f>;
|
||||
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
|
||||
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
|
||||
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
|
||||
<0 0 0 2 &pcie3x4_intc 1>,
|
||||
<0 0 0 3 &pcie3x4_intc 2>,
|
||||
<0 0 0 4 &pcie3x4_intc 3>;
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x0000 &its1 0x0000 0x1000>;
|
||||
num-lanes = <4>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40000000 0x0 0x00400000>,
|
||||
<0x0 0xfe150000 0x0 0x00010000>,
|
||||
<0x0 0xf0000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
reset-names = "pwr", "pipe";
|
||||
status = "disabled";
|
||||
|
||||
pcie3x4_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3x2: pcie@fe160000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x10 0x1f>;
|
||||
clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
|
||||
<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
|
||||
<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
||||
<0 0 0 2 &pcie3x2_intc 1>,
|
||||
<0 0 0 3 &pcie3x2_intc 2>,
|
||||
<0 0 0 4 &pcie3x2_intc 3>;
|
||||
linux,pci-domain = <1>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x1000 &its1 0x1000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40400000 0x0 0x00400000>,
|
||||
<0x0 0xfe160000 0x0 0x00010000>,
|
||||
<0x0 0xf1000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
reset-names = "pwr", "pipe";
|
||||
status = "disabled";
|
||||
|
||||
pcie3x2_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2x1l0: pcie@fe170000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
|
||||
<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
|
||||
<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
|
||||
<0 0 0 2 &pcie2x1l0_intc 1>,
|
||||
<0 0 0 3 &pcie2x1l0_intc 2>,
|
||||
<0 0 0 4 &pcie2x1l0_intc 3>;
|
||||
linux,pci-domain = <2>;
|
||||
max-link-speed = <2>;
|
||||
msi-map = <0x2000 &its0 0x2000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy1_ps PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40800000 0x0 0x00400000>,
|
||||
<0x0 0xfe170000 0x0 0x00010000>,
|
||||
<0x0 0xf2000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2x1l0_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: ethernet@fe1b0000 {
|
||||
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe1b0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
|
||||
<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
|
||||
<&cru CLK_GMAC0_PTP_REF>;
|
||||
clock-names = "stmmaceth", "clk_mac_ref",
|
||||
"pclk_mac", "aclk_mac",
|
||||
"ptp_ref";
|
||||
power-domains = <&power RK3588_PD_GMAC>;
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,php-grf = <&php_grf>;
|
||||
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
snps,mixed-burst;
|
||||
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
snps,tso;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
};
|
||||
|
||||
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,blen = <0 0 0 0 16 8 4>;
|
||||
snps,wr_osr_lmt = <4>;
|
||||
snps,rd_osr_lmt = <8>;
|
||||
};
|
||||
|
||||
gmac0_mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <2>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
};
|
||||
|
||||
gmac0_mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <2>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
};
|
||||
};
|
||||
|
||||
sata1: sata@fe220000 {
|
||||
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfe220000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
|
||||
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
|
||||
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
|
||||
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
||||
ports-implemented = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
sata-port@0 {
|
||||
reg = <0>;
|
||||
hba-port-cap = <HBA_PORT_FBSCP>;
|
||||
phys = <&combphy1_ps PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
snps,rx-ts-max = <32>;
|
||||
snps,tx-ts-max = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
usbdp_phy1: phy@fed90000 {
|
||||
compatible = "rockchip,rk3588-usbdp-phy";
|
||||
reg = <0x0 0xfed90000 0x0 0x10000>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
<&cru CLK_USBDP_PHY1_IMMORTAL>,
|
||||
<&cru PCLK_USBDPPHY1>,
|
||||
<&u2phy1>;
|
||||
clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
||||
<&cru SRST_P_USBDPPHY1>;
|
||||
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
rockchip,u2phy-grf = <&usb2phy1_grf>;
|
||||
rockchip,usb-grf = <&usb_grf>;
|
||||
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
combphy1_ps: phy@fee10000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee10000 0x0 0x100>;
|
||||
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
|
||||
<&cru PCLK_PHP_ROOT>;
|
||||
clock-names = "ref", "apb", "pipe";
|
||||
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
#phy-cells = <1>;
|
||||
resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
|
||||
reset-names = "phy", "apb";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie30phy: phy@fee80000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy";
|
||||
reg = <0x0 0xfee80000 0x0 0x20000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
|
||||
clock-names = "pclk";
|
||||
resets = <&cru SRST_PCIE30_PHY>;
|
||||
reset-names = "phy";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,phy-grf = <&pcie30_phy_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
#include "rk3588-extra.dtsi"
|
||||
|
||||
@ -4,4 +4,4 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3588.dtsi"
|
||||
#include "rk3588-extra.dtsi"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user