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net: ethernet: mtk_eth_soc: ppe: add support for multiple PPEs
Add the missing pieces to allow multiple PPEs units, one for each GMAC. mtk_gdm_config has been modified to work on targted mac ID, the inner loop moved outside of the function to allow unrelated operations like setting the MAC's PPE index. Introduce a sanity check in flow_offload_replace to account for non-MTK ingress devices. Additional field 'ppe_idx' was added to struct mtk_mac in order to keep track on the assigned PPE unit. Signed-off-by: Elad Yifee <eladwf@gmail.com> Link: https://lore.kernel.org/r/20240607082155.20021-1-eladwf@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
parent
05f43db7f0
commit
dee4dd10c7
@ -80,7 +80,9 @@ static const struct mtk_reg_map mtk_reg_map = {
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.fq_blen = 0x1b2c,
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},
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.gdm1_cnt = 0x2400,
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.gdma_to_ppe = 0x4444,
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.gdma_to_ppe = {
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[0] = 0x4444,
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},
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.ppe_base = 0x0c00,
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.wdma_base = {
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[0] = 0x2800,
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@ -144,7 +146,10 @@ static const struct mtk_reg_map mt7986_reg_map = {
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.tx_sch_rate = 0x4798,
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},
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.gdm1_cnt = 0x1c00,
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.gdma_to_ppe = 0x3333,
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.gdma_to_ppe = {
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[0] = 0x3333,
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[1] = 0x4444,
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},
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.ppe_base = 0x2000,
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.wdma_base = {
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[0] = 0x4800,
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@ -192,7 +197,11 @@ static const struct mtk_reg_map mt7988_reg_map = {
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.tx_sch_rate = 0x4798,
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},
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.gdm1_cnt = 0x1c00,
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.gdma_to_ppe = 0x3333,
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.gdma_to_ppe = {
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[0] = 0x3333,
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[1] = 0x4444,
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[2] = 0xcccc,
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},
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.ppe_base = 0x2000,
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.wdma_base = {
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[0] = 0x4800,
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@ -2015,6 +2024,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
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struct mtk_rx_dma_v2 *rxd, trxd;
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int done = 0, bytes = 0;
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dma_addr_t dma_addr = DMA_MAPPING_ERROR;
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int ppe_idx = 0;
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while (done < budget) {
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unsigned int pktlen, *rxdcsum;
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@ -2058,6 +2068,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
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goto release_desc;
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netdev = eth->netdev[mac];
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ppe_idx = eth->mac[mac]->ppe_idx;
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if (unlikely(test_bit(MTK_RESETTING, ð->state)))
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goto release_desc;
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@ -2181,7 +2192,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
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}
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if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
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mtk_ppe_check_skb(eth->ppe[0], skb, hash);
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mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash);
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skb_record_rx_queue(skb, 0);
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napi_gro_receive(napi, skb);
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@ -3276,37 +3287,27 @@ static int mtk_start_dma(struct mtk_eth *eth)
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return 0;
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}
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static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
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static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config)
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{
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int i;
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u32 val;
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
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return;
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for (i = 0; i < MTK_MAX_DEVS; i++) {
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u32 val;
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val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id));
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if (!eth->netdev[i])
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continue;
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/* default setup the forward port to send frame to PDMA */
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val &= ~0xffff;
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val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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/* Enable RX checksum */
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val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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/* default setup the forward port to send frame to PDMA */
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val &= ~0xffff;
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val |= config;
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/* Enable RX checksum */
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val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id]))
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val |= MTK_GDMA_SPECIAL_TAG;
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val |= config;
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if (netdev_uses_dsa(eth->netdev[i]))
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val |= MTK_GDMA_SPECIAL_TAG;
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mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
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}
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/* Reset and enable PSE */
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mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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mtk_w32(eth, 0, MTK_RST_GL);
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mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id));
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}
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@ -3366,7 +3367,10 @@ static int mtk_open(struct net_device *dev)
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{
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struct mtk_mac *mac = netdev_priv(dev);
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struct mtk_eth *eth = mac->hw;
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int i, err;
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struct mtk_mac *target_mac;
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int i, err, ppe_num;
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ppe_num = eth->soc->ppe_num;
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err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
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if (err) {
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@ -3390,18 +3394,38 @@ static int mtk_open(struct net_device *dev)
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for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
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mtk_ppe_start(eth->ppe[i]);
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gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe
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: MTK_GDMA_TO_PDMA;
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mtk_gdm_config(eth, gdm_config);
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for (i = 0; i < MTK_MAX_DEVS; i++) {
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if (!eth->netdev[i])
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break;
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target_mac = netdev_priv(eth->netdev[i]);
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if (!soc->offload_version) {
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target_mac->ppe_idx = 0;
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gdm_config = MTK_GDMA_TO_PDMA;
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} else if (ppe_num >= 3 && target_mac->id == 2) {
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target_mac->ppe_idx = 2;
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gdm_config = soc->reg_map->gdma_to_ppe[2];
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} else if (ppe_num >= 2 && target_mac->id == 1) {
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target_mac->ppe_idx = 1;
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gdm_config = soc->reg_map->gdma_to_ppe[1];
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} else {
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target_mac->ppe_idx = 0;
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gdm_config = soc->reg_map->gdma_to_ppe[0];
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}
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mtk_gdm_config(eth, target_mac->id, gdm_config);
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}
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/* Reset and enable PSE */
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mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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mtk_w32(eth, 0, MTK_RST_GL);
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napi_enable(ð->tx_napi);
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napi_enable(ð->rx_napi);
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mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
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mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
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refcount_set(ð->dma_refcnt, 1);
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}
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else
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} else {
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refcount_inc(ð->dma_refcnt);
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}
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phylink_start(mac->phylink);
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netif_tx_start_all_queues(dev);
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@ -3478,7 +3502,8 @@ static int mtk_stop(struct net_device *dev)
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if (!refcount_dec_and_test(ð->dma_refcnt))
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return 0;
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mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
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for (i = 0; i < MTK_MAX_DEVS; i++)
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mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL);
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mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
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mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
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@ -4959,23 +4984,24 @@ static int mtk_probe(struct platform_device *pdev)
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}
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if (eth->soc->offload_version) {
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u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1;
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u8 ppe_num = eth->soc->ppe_num;
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num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
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for (i = 0; i < num_ppe; i++) {
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u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
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ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num);
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for (i = 0; i < ppe_num; i++) {
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u32 ppe_addr = eth->soc->reg_map->ppe_base;
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ppe_addr += (i == 2 ? 0xc00 : i * 0x400);
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eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
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if (!eth->ppe[i]) {
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err = -ENOMEM;
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goto err_deinit_ppe;
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}
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}
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err = mtk_eth_offload_init(eth, i);
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err = mtk_eth_offload_init(eth);
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if (err)
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goto err_deinit_ppe;
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if (err)
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goto err_deinit_ppe;
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}
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}
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for (i = 0; i < MTK_MAX_DEVS; i++) {
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@ -5083,6 +5109,7 @@ static const struct mtk_soc_data mt7621_data = {
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.required_pctl = false,
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.version = 1,
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.offload_version = 1,
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.ppe_num = 1,
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.hash_offset = 2,
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.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
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.tx = {
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@ -5111,6 +5138,7 @@ static const struct mtk_soc_data mt7622_data = {
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.required_pctl = false,
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.version = 1,
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.offload_version = 2,
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.ppe_num = 1,
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.hash_offset = 2,
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.has_accounting = true,
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.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
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@ -5139,6 +5167,7 @@ static const struct mtk_soc_data mt7623_data = {
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.required_pctl = true,
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.version = 1,
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.offload_version = 1,
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.ppe_num = 1,
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.hash_offset = 2,
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.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
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.disable_pll_modes = true,
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@ -5194,6 +5223,7 @@ static const struct mtk_soc_data mt7981_data = {
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.required_pctl = false,
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.version = 2,
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.offload_version = 2,
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.ppe_num = 2,
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.hash_offset = 4,
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.has_accounting = true,
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.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
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@ -5223,6 +5253,7 @@ static const struct mtk_soc_data mt7986_data = {
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.required_pctl = false,
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.version = 2,
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.offload_version = 2,
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.ppe_num = 2,
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.hash_offset = 4,
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.has_accounting = true,
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.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
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@ -5252,6 +5283,7 @@ static const struct mtk_soc_data mt7988_data = {
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.required_pctl = false,
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.version = 3,
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.offload_version = 2,
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.ppe_num = 3,
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.hash_offset = 4,
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.has_accounting = true,
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.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
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@ -1132,7 +1132,7 @@ struct mtk_reg_map {
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u32 tx_sch_rate; /* tx scheduler rate control registers */
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} qdma;
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u32 gdm1_cnt;
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u32 gdma_to_ppe;
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u32 gdma_to_ppe[3];
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u32 ppe_base;
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u32 wdma_base[3];
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u32 pse_iq_sta;
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@ -1170,6 +1170,7 @@ struct mtk_soc_data {
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u8 offload_version;
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u8 hash_offset;
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u8 version;
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u8 ppe_num;
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u16 foe_entry_size;
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netdev_features_t hw_features;
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bool has_accounting;
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@ -1294,7 +1295,7 @@ struct mtk_eth {
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struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS];
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struct mtk_ppe *ppe[2];
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struct mtk_ppe *ppe[3];
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struct rhashtable flow_table;
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struct bpf_prog __rcu *prog;
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@ -1319,6 +1320,7 @@ struct mtk_eth {
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struct mtk_mac {
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int id;
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phy_interface_t interface;
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u8 ppe_idx;
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int speed;
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struct device_node *of_node;
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struct phylink *phylink;
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@ -1440,7 +1442,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
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int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
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int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
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int mtk_eth_offload_init(struct mtk_eth *eth);
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int mtk_eth_offload_init(struct mtk_eth *eth, u8 id);
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int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
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void *type_data);
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int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls,
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@ -245,10 +245,10 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f,
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int ppe_index)
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{
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struct flow_rule *rule = flow_cls_offload_flow_rule(f);
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struct net_device *idev = NULL, *odev = NULL;
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struct flow_action_entry *act;
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struct mtk_flow_data data = {};
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struct mtk_foe_entry foe;
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struct net_device *odev = NULL;
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struct mtk_flow_entry *entry;
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int offload_type = 0;
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int wed_index = -1;
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@ -264,6 +264,17 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f,
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struct flow_match_meta match;
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flow_rule_match_meta(rule, &match);
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if (mtk_is_netsys_v2_or_greater(eth)) {
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idev = __dev_get_by_index(&init_net, match.key->ingress_ifindex);
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if (idev) {
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struct mtk_mac *mac = netdev_priv(idev);
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if (WARN_ON(mac->ppe_idx >= eth->soc->ppe_num))
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return -EINVAL;
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ppe_index = mac->ppe_idx;
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}
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}
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} else {
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return -EOPNOTSUPP;
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}
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@ -637,7 +648,9 @@ int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
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}
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}
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int mtk_eth_offload_init(struct mtk_eth *eth)
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int mtk_eth_offload_init(struct mtk_eth *eth, u8 id)
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{
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if (!eth->ppe[id] || !eth->ppe[id]->foe_table)
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return 0;
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return rhashtable_init(ð->flow_table, &mtk_flow_ht_params);
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}
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