Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-28 15:11:31 +00:00
Code Issues Packages Projects Releases Wiki Activity

drm/i915: move skl_preferred_vco_freq to display substruct

Browse Source 
The info is related to display, and should be placed under
i915->display.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4e9877d1641bce905cc9dd5eabe40df51ddbe9b5.1712599670.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2024-04-09 10:18:51 +03:00
parent 87816d6074
commit ded402c7a0
4 changed files with 10 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@ -1021,15 +1021,14 @@ static int skl_cdclk_decimal(int cdclk)
return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
}
static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
int vco)
static void skl_set_preferred_cdclk_vco(struct drm_i915_private *i915, int vco)
{
bool changed = dev_priv->skl_preferred_vco_freq != vco;
bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco;
dev_priv->skl_preferred_vco_freq = vco;
i915->display.cdclk.skl_preferred_vco_freq = vco;
if (changed)
intel_update_max_cdclk(dev_priv);
intel_update_max_cdclk(i915);
}
static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
@ -1233,7 +1232,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
* Use the current vco as our initial
* guess as to what the preferred vco is.
*/
if (dev_priv->skl_preferred_vco_freq == 0)
if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0)
skl_set_preferred_cdclk_vco(dev_priv,
dev_priv->display.cdclk.hw.vco);
return;
@ -1241,7 +1240,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
cdclk_config.vco = 8100000;
cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
@ -3011,7 +3010,7 @@ static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
vco = cdclk_state->logical.vco;
if (!vco)
vco = dev_priv->skl_preferred_vco_freq;
vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
if (!crtc_state->hw.enable)
@ -3397,7 +3396,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
vco = dev_priv->skl_preferred_vco_freq;
vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
/*

1
drivers/gpu/drm/i915/display/intel_display_core.h
View File

@ -345,6 +345,7 @@ struct intel_display {
struct intel_global_obj obj;
unsigned int max_cdclk_freq;
unsigned int skl_preferred_vco_freq;
} cdclk;
struct {

1
drivers/gpu/drm/i915/i915_drv.h
View File

@ -251,7 +251,6 @@ struct drm_i915_private {
bool preserve_bios_swizzle;
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;

5
drivers/gpu/drm/xe/xe_device_types.h
View File

@ -498,10 +498,7 @@ struct xe_device {
struct mutex sb_lock;
/* Should be in struct intel_display */
u32 skl_preferred_vco_freq, max_dotclk_freq, hti_state;
u8 snps_phy_failed_calibration;
struct drm_atomic_state *modeset_restore_state;
struct list_head global_obj_list;
u32 max_dotclk_freq;
union {
/* only to allow build, not used functionally */