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mtd: brcmnand: Add v7.2 controller support
The 7.2 controller differs in a few area compared to its predecssor (7.1): - NAND scrambler, which we are not using just yet - higher ECC levels (up to 120 bits) per 1KB data blocks, also not supported yet - up to 128B OOB This patch adds the necessary code to support such a controller generation and updates the Device Tree binding. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Kamal Dasu <kdasu.kdev@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Florian Fainelli
Boris Brezillon
parent
cabfeaa678
commit
decba6d478
@ -27,6 +27,7 @@ Required properties:
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brcm,brcmnand-v6.2
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brcm,brcmnand-v7.0
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brcm,brcmnand-v7.1
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brcm,brcmnand-v7.2
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brcm,brcmnand
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- reg : the register start and length for NAND register region.
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(optional) Flash DMA register range (if present)
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@ -340,6 +340,36 @@ static const u16 brcmnand_regs_v71[] = {
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[BRCMNAND_FC_BASE] = 0x400,
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};
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/* BRCMNAND v7.2 */
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static const u16 brcmnand_regs_v72[] = {
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[BRCMNAND_CMD_START] = 0x04,
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[BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
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[BRCMNAND_CMD_ADDRESS] = 0x0c,
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[BRCMNAND_INTFC_STATUS] = 0x14,
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[BRCMNAND_CS_SELECT] = 0x18,
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[BRCMNAND_CS_XOR] = 0x1c,
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[BRCMNAND_LL_OP] = 0x20,
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[BRCMNAND_CS0_BASE] = 0x50,
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[BRCMNAND_CS1_BASE] = 0,
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[BRCMNAND_CORR_THRESHOLD] = 0xdc,
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[BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
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[BRCMNAND_UNCORR_COUNT] = 0xfc,
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[BRCMNAND_CORR_COUNT] = 0x100,
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[BRCMNAND_CORR_EXT_ADDR] = 0x10c,
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[BRCMNAND_CORR_ADDR] = 0x110,
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[BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
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[BRCMNAND_UNCORR_ADDR] = 0x118,
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[BRCMNAND_SEMAPHORE] = 0x150,
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[BRCMNAND_ID] = 0x194,
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[BRCMNAND_ID_EXT] = 0x198,
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[BRCMNAND_LL_RDATA] = 0x19c,
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[BRCMNAND_OOB_READ_BASE] = 0x200,
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[BRCMNAND_OOB_READ_10_BASE] = 0,
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[BRCMNAND_OOB_WRITE_BASE] = 0x400,
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[BRCMNAND_OOB_WRITE_10_BASE] = 0,
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[BRCMNAND_FC_BASE] = 0x600,
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};
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enum brcmnand_cs_reg {
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BRCMNAND_CS_CFG_EXT = 0,
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BRCMNAND_CS_CFG,
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@ -435,7 +465,9 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
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}
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/* Register offsets */
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if (ctrl->nand_version >= 0x0701)
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if (ctrl->nand_version >= 0x0702)
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ctrl->reg_offsets = brcmnand_regs_v72;
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else if (ctrl->nand_version >= 0x0701)
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ctrl->reg_offsets = brcmnand_regs_v71;
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else if (ctrl->nand_version >= 0x0600)
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ctrl->reg_offsets = brcmnand_regs_v60;
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@ -480,7 +512,9 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
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}
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/* Maximum spare area sector size (per 512B) */
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if (ctrl->nand_version >= 0x0600)
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if (ctrl->nand_version >= 0x0702)
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ctrl->max_oob = 128;
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else if (ctrl->nand_version >= 0x0600)
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ctrl->max_oob = 64;
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else if (ctrl->nand_version >= 0x0500)
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ctrl->max_oob = 32;
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@ -583,14 +617,20 @@ static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
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enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
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int cs = host->cs;
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if (ctrl->nand_version >= 0x0600)
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if (ctrl->nand_version >= 0x0702)
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bits = 7;
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else if (ctrl->nand_version >= 0x0600)
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bits = 6;
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else if (ctrl->nand_version >= 0x0500)
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bits = 5;
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else
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bits = 4;
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if (ctrl->nand_version >= 0x0600) {
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if (ctrl->nand_version >= 0x0702) {
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if (cs >= 4)
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reg = BRCMNAND_CORR_THRESHOLD_EXT;
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shift = (cs % 4) * bits;
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} else if (ctrl->nand_version >= 0x0600) {
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if (cs >= 5)
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reg = BRCMNAND_CORR_THRESHOLD_EXT;
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shift = (cs % 5) * bits;
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@ -631,19 +671,28 @@ enum {
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static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
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{
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if (ctrl->nand_version >= 0x0600)
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if (ctrl->nand_version >= 0x0702)
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return GENMASK(7, 0);
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else if (ctrl->nand_version >= 0x0600)
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return GENMASK(6, 0);
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else
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return GENMASK(5, 0);
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}
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#define NAND_ACC_CONTROL_ECC_SHIFT 16
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#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13
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static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
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{
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u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
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return mask << NAND_ACC_CONTROL_ECC_SHIFT;
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mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
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/* v7.2 includes additional ECC levels */
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if (ctrl->nand_version >= 0x0702)
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mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
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return mask;
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}
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static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
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@ -667,7 +716,9 @@ static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
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static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
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{
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if (ctrl->nand_version >= 0x0600)
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if (ctrl->nand_version >= 0x0702)
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return 9;
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else if (ctrl->nand_version >= 0x0600)
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return 7;
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else if (ctrl->nand_version >= 0x0500)
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return 6;
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@ -773,10 +824,16 @@ enum brcmnand_llop_type {
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* Internal support functions
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***********************************************************************/
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static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
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static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
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struct brcmnand_cfg *cfg)
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{
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return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
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cfg->ecc_level == 15;
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if (ctrl->nand_version <= 0x0701)
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return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
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cfg->ecc_level == 15;
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else
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return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
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cfg->ecc_level == 15) ||
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(cfg->spare_area_size == 28 && cfg->ecc_level == 16));
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}
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/*
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@ -931,7 +988,7 @@ static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
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if (p->sector_size_1k)
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ecc_level <<= 1;
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if (is_hamming_ecc(p)) {
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if (is_hamming_ecc(host->ctrl, p)) {
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ecc->bytes = 3 * sectors;
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mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
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return 0;
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@ -1857,7 +1914,8 @@ static int brcmnand_set_cfg(struct brcmnand_host *host,
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return 0;
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}
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static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
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static void brcmnand_print_cfg(struct brcmnand_host *host,
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char *buf, struct brcmnand_cfg *cfg)
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{
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buf += sprintf(buf,
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"%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
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@ -1868,7 +1926,7 @@ static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
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cfg->spare_area_size, cfg->device_width);
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/* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
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if (is_hamming_ecc(cfg))
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if (is_hamming_ecc(host->ctrl, cfg))
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sprintf(buf, ", Hamming ECC");
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else if (cfg->sector_size_1k)
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sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
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@ -1987,7 +2045,7 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
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brcmnand_set_ecc_enabled(host, 1);
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brcmnand_print_cfg(msg, cfg);
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brcmnand_print_cfg(host, msg, cfg);
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dev_info(ctrl->dev, "detected %s\n", msg);
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/* Configure ACC_CONTROL */
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@ -1995,6 +2053,10 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
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tmp = nand_readreg(ctrl, offs);
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tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
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tmp &= ~ACC_CONTROL_RD_ERASED;
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/* We need to turn on Read from erased paged protected by ECC */
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if (ctrl->nand_version >= 0x0702)
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tmp |= ACC_CONTROL_RD_ERASED;
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tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
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if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
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/*
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@ -2195,6 +2257,7 @@ static const struct of_device_id brcmnand_of_match[] = {
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{ .compatible = "brcm,brcmnand-v6.2" },
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{ .compatible = "brcm,brcmnand-v7.0" },
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{ .compatible = "brcm,brcmnand-v7.1" },
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{ .compatible = "brcm,brcmnand-v7.2" },
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{},
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};
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MODULE_DEVICE_TABLE(of, brcmnand_of_match);
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