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ARM: l2c: omap2: remove cache size override

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The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2014-03-17 16:53:31 +00:00
parent 7eab0039d3
commit deb125abad
1 changed files with 3 additions and 5 deletions
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8
arch/arm/mach-omap2/omap4-common.c
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@ -213,20 +213,18 @@ static int __init omap_l2_cache_init(void)
return -ENOMEM;
/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
aux_ctrl = L310_AUX_CTRL_ASSOCIATIVITY_16 |
L310_AUX_CTRL_CACHE_REPLACE_RR |
aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR |
L310_AUX_CTRL_NS_LOCKDOWN |
L310_AUX_CTRL_NS_INT_CTRL |
L2C_AUX_CTRL_WAY_SIZE(3) |
L2C_AUX_CTRL_SHARED_OVERRIDE |
L310_AUX_CTRL_DATA_PREFETCH |
L310_AUX_CTRL_INSTR_PREFETCH;
outer_cache.write_sec = omap4_l2c310_write_sec;
if (of_have_populated_dt())
l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
l2x0_of_init(aux_ctrl, 0xc19fffff);
else
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
l2x0_init(l2cache_base, aux_ctrl, 0xc19fffff);
return 0;
}