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MIPS: asm: r4kcache: Add EVA cache flushing functions
Add EVA cache flushing functions similar to non-EVA configurations. Because the cache may or may not contain user virtual addresses, we need to use the 'cache' or 'cachee' instruction based on whether we flush the cache on behalf of kernel or user respectively. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Leonid Yegoshin
Ralf Baechle
parent
a805385499
commit
de8974e3f7
@ -17,6 +17,7 @@
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#include <asm/cpu-features.h>
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#include <asm/cpu-type.h>
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#include <asm/mipsmtregs.h>
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#include <asm/uaccess.h> /* for segment_eq() */
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/*
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* This macro return a properly sign-extended address suitable as base address
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@ -374,6 +375,91 @@ static inline void invalidate_tcache_page(unsigned long addr)
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: "r" (base), \
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"i" (op));
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/*
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* Perform the cache operation specified by op using a user mode virtual
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* address while in kernel mode.
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*/
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#define cache16_unroll32_user(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips0 \n" \
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" .set eva \n" \
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" cachee %1, 0x000(%0); cachee %1, 0x010(%0) \n" \
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" cachee %1, 0x020(%0); cachee %1, 0x030(%0) \n" \
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" cachee %1, 0x040(%0); cachee %1, 0x050(%0) \n" \
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" cachee %1, 0x060(%0); cachee %1, 0x070(%0) \n" \
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" cachee %1, 0x080(%0); cachee %1, 0x090(%0) \n" \
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" cachee %1, 0x0a0(%0); cachee %1, 0x0b0(%0) \n" \
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" cachee %1, 0x0c0(%0); cachee %1, 0x0d0(%0) \n" \
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" cachee %1, 0x0e0(%0); cachee %1, 0x0f0(%0) \n" \
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" cachee %1, 0x100(%0); cachee %1, 0x110(%0) \n" \
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" cachee %1, 0x120(%0); cachee %1, 0x130(%0) \n" \
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" cachee %1, 0x140(%0); cachee %1, 0x150(%0) \n" \
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" cachee %1, 0x160(%0); cachee %1, 0x170(%0) \n" \
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" cachee %1, 0x180(%0); cachee %1, 0x190(%0) \n" \
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" cachee %1, 0x1a0(%0); cachee %1, 0x1b0(%0) \n" \
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" cachee %1, 0x1c0(%0); cachee %1, 0x1d0(%0) \n" \
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" cachee %1, 0x1e0(%0); cachee %1, 0x1f0(%0) \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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#define cache32_unroll32_user(base, op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips0 \n" \
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" .set eva \n" \
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" cachee %1, 0x000(%0); cachee %1, 0x020(%0) \n" \
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" cachee %1, 0x040(%0); cachee %1, 0x060(%0) \n" \
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" cachee %1, 0x080(%0); cachee %1, 0x0a0(%0) \n" \
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" cachee %1, 0x0c0(%0); cachee %1, 0x0e0(%0) \n" \
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" cachee %1, 0x100(%0); cachee %1, 0x120(%0) \n" \
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" cachee %1, 0x140(%0); cachee %1, 0x160(%0) \n" \
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" cachee %1, 0x180(%0); cachee %1, 0x1a0(%0) \n" \
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" cachee %1, 0x1c0(%0); cachee %1, 0x1e0(%0) \n" \
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" cachee %1, 0x200(%0); cachee %1, 0x220(%0) \n" \
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" cachee %1, 0x240(%0); cachee %1, 0x260(%0) \n" \
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" cachee %1, 0x280(%0); cachee %1, 0x2a0(%0) \n" \
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" cachee %1, 0x2c0(%0); cachee %1, 0x2e0(%0) \n" \
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" cachee %1, 0x300(%0); cachee %1, 0x320(%0) \n" \
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" cachee %1, 0x340(%0); cachee %1, 0x360(%0) \n" \
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" cachee %1, 0x380(%0); cachee %1, 0x3a0(%0) \n" \
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" cachee %1, 0x3c0(%0); cachee %1, 0x3e0(%0) \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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#define cache64_unroll32_user(base, op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips0 \n" \
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" .set eva \n" \
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" cachee %1, 0x000(%0); cachee %1, 0x040(%0) \n" \
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" cachee %1, 0x080(%0); cachee %1, 0x0c0(%0) \n" \
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" cachee %1, 0x100(%0); cachee %1, 0x140(%0) \n" \
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" cachee %1, 0x180(%0); cachee %1, 0x1c0(%0) \n" \
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" cachee %1, 0x200(%0); cachee %1, 0x240(%0) \n" \
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" cachee %1, 0x280(%0); cachee %1, 0x2c0(%0) \n" \
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" cachee %1, 0x300(%0); cachee %1, 0x340(%0) \n" \
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" cachee %1, 0x380(%0); cachee %1, 0x3c0(%0) \n" \
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" cachee %1, 0x400(%0); cachee %1, 0x440(%0) \n" \
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" cachee %1, 0x480(%0); cachee %1, 0x4c0(%0) \n" \
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" cachee %1, 0x500(%0); cachee %1, 0x540(%0) \n" \
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" cachee %1, 0x580(%0); cachee %1, 0x5c0(%0) \n" \
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" cachee %1, 0x600(%0); cachee %1, 0x640(%0) \n" \
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" cachee %1, 0x680(%0); cachee %1, 0x6c0(%0) \n" \
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" cachee %1, 0x700(%0); cachee %1, 0x740(%0) \n" \
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" cachee %1, 0x780(%0); cachee %1, 0x7c0(%0) \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
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#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
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static inline void extra##blast_##pfx##cache##lsize(void) \
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@ -447,6 +533,32 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
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#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
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{ \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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__##pfx##flush_prologue \
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\
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do { \
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cache##lsize##_unroll32_user(start, hitop); \
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start += lsize * 32; \
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} while (start < end); \
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\
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__##pfx##flush_epilogue \
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}
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
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16)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
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32)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
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64)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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/* build blast_xxx_range, protected_blast_xxx_range */
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#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
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static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
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@ -468,9 +580,47 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
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__##pfx##flush_epilogue \
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}
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#ifndef CONFIG_EVA
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
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#else
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#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop) \
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static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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\
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__##pfx##flush_prologue \
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\
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if (segment_eq(get_fs(), USER_DS)) { \
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while (1) { \
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protected_cachee_op(hitop, addr); \
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if (addr == aend) \
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break; \
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addr += lsize; \
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} \
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} else { \
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while (1) { \
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protected_cache_op(hitop, addr); \
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if (addr == aend) \
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break; \
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addr += lsize; \
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} \
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\
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} \
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__##pfx##flush_epilogue \
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}
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__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
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__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
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#endif
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
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protected_, loongson2_)
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
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