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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx into merge
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commit
de60fba2bb
@ -3375,7 +3375,7 @@ P: Matt Porter
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M: mporter@kernel.crashing.org
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W: http://www.penguinppc.org/
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L: linuxppc-dev@ozlabs.org
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc.git
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
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S: Maintained
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LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
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@ -158,6 +158,46 @@ void ibm440spe_fixup_memsize(void)
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#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
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/*
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* Some U-Boot versions set the number of chipselects to two
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* for Sequoia/Rainier boards while they only have one chipselect
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* hardwired. Hardcode the number of chipselects to one
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* for sequioa/rainer board models or read the actual value
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* from the memory controller register DDR0_10 otherwise.
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*/
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static inline u32 ibm4xx_denali_get_cs(void)
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{
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void *devp;
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char model[64];
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u32 val, cs;
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devp = finddevice("/");
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if (!devp)
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goto read_cs;
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if (getprop(devp, "model", model, sizeof(model)) <= 0)
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goto read_cs;
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model[sizeof(model)-1] = 0;
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if (!strcmp(model, "amcc,sequoia") ||
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!strcmp(model, "amcc,rainier"))
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return 1;
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read_cs:
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/* get CS value */
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val = SDRAM0_READ(DDR0_10);
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val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
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cs = 0;
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while (val) {
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if (val & 0x1)
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cs++;
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val = val >> 1;
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}
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return cs;
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}
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void ibm4xx_denali_fixup_memsize(void)
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{
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u32 val, max_cs, max_col, max_row;
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@ -173,17 +213,7 @@ void ibm4xx_denali_fixup_memsize(void)
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max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
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max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
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/* get CS value */
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val = SDRAM0_READ(DDR0_10);
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val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
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cs = 0;
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while (val) {
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if (val & 0x1)
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cs++;
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val = val >> 1;
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}
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cs = ibm4xx_denali_get_cs();
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if (!cs)
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fatal("No memory installed\n");
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if (cs > max_cs)
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@ -193,9 +223,9 @@ void ibm4xx_denali_fixup_memsize(void)
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val = SDRAM0_READ(DDR0_14);
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if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
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dpath = 8; /* 64 bits */
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else
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dpath = 4; /* 32 bits */
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else
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dpath = 8; /* 64 bits */
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/* get address pins (rows) */
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val = SDRAM0_READ(DDR0_42);
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