A few clk driver fixes for the merge window to fix the build and boot on

some SoCs.
 
  - Initialize struct clk_init_data in the TI da8xx-cfgchip driver so
    that stack contents aren't used for things like clk flags leading to
    unexpected behavior
 
  - Don't leak stack contents in a debug print in the new Sophgo clk
    driver
 
  - Disable the new T-Head clk driver on 32-bit targets to fix the build
    due to a division
 
  - Fix Samsung Exynos4 fin_pll wreckage from the clkdev rework done last
    cycle by using a struct clk_hw directly instead of a struct clk
    consumer
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmaj7w8RHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSVJbRAAkyHgShvwM/pnjVKAD6F5p6gUd3S7RnS8
 gaV77KUthhWzNE8TXneGA20RUNUYgRbIWSC3YWA1V8p4sb8d8SGMPDxzcFuEa4eq
 qLBvb3lNcynyhpfMErRpVvF5EZxqdJkGJdSgF+QzYZLJL28Bff3eKwNM7K6cgl41
 W4Je2E4dmifqqeOwWl/1YiAh/GN03C470q4DP9Jekeqn5nZie4ZNttD72XIhywSS
 i11tWQ5E4JBcGkg0beCwwsiDo/Snpzt1JOtCuargbn3IupAiUcZJayycE8sUFJ/U
 Ath/ZJerBEPYzmcHfwg9JKnaDFPucaOkszcAxysZvNYerjvD/jZG64C1nnl4KURt
 DUlYNxjzbzQ3Byr1182D4tFOOUi0XzR5SG2lv/6syv6nDifIuzjz5AVIQDHweJb1
 49j40HdzpzdBQjicepIf+g96Ej+5qVaIoHgBZPMxsEli95VfITTzb+K+Uv4UjkxG
 o8BYm3IJKUvF1E3tnjswVjG2Lm9xMfm674WwJs7uUKHYy7Y+b8g8a9yuSz1rhL0d
 0jZ1yyBIhqJe9UVGB3YUOOxu//W/r9do1bsAj0rCGR5m/D0XPNj63NuOBQUzdGZ8
 c+xIL2GYfGkcprkEVznU29AOoxnl47bzwW1C2Y4G7w2kuh3lNXq+9N2Mpe4+juE4
 C5M6xdxmeCI=
 =tIM4
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A few clk driver fixes for the merge window to fix the build and boot
  on some SoCs.

   - Initialize struct clk_init_data in the TI da8xx-cfgchip driver so
     that stack contents aren't used for things like clk flags leading
     to unexpected behavior

   - Don't leak stack contents in a debug print in the new Sophgo clk
     driver

   - Disable the new T-Head clk driver on 32-bit targets to fix the
     build due to a division

   - Fix Samsung Exynos4 fin_pll wreckage from the clkdev rework done
     last cycle by using a struct clk_hw directly instead of a struct
     clk consumer"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: samsung: fix getting Exynos4 fin_pll rate from external clocks
  clk: T-Head: Disable on 32-bit Targets
  clk: sophgo: clk-sg2042-pll: Fix uninitialized variable in debug output
  clk: davinci: da8xx-cfgchip: Initialize clk_init_data before use

drivers/clk/davinci/da8xx-cfgchip.c

@@ -508,7 +508,7 @@ da8xx_cfgchip_register_usb0_clk48(struct device *dev,
 	const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" };
 	struct clk *fck_clk;
 	struct da8xx_usb0_clk48 *usb0;
-	struct clk_init_data init;
+	struct clk_init_data init = {};
 	int ret;
 
 	fck_clk = devm_clk_get(dev, "fck");
@@ -583,7 +583,7 @@ da8xx_cfgchip_register_usb1_clk48(struct device *dev,
 {
 	const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" };
 	struct da8xx_usb1_clk48 *usb1;
-	struct clk_init_data init;
+	struct clk_init_data init = {};
 	int ret;
 
 	usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL);

drivers/clk/samsung/clk-exynos4.c

@@ -1040,19 +1040,20 @@ static unsigned long __init exynos4_get_xom(void)
 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
 {
 	struct samsung_fixed_rate_clock fclk;
-	struct clk *clk;
-	unsigned long finpll_f = 24000000;
+	unsigned long finpll_f;
+	unsigned int parent;
 	char *parent_name;
 	unsigned int xom = exynos4_get_xom();
 
 	parent_name = xom & 1 ? "xusbxti" : "xxti";
-	clk = clk_get(NULL, parent_name);
-	if (IS_ERR(clk)) {
+	parent = xom & 1 ? CLK_XUSBXTI : CLK_XXTI;
+
+	finpll_f = clk_hw_get_rate(ctx->clk_data.hws[parent]);
+	if (!finpll_f) {
 		pr_err("%s: failed to lookup parent clock %s, assuming "
 			"fin_pll clock frequency is 24MHz\n", __func__,
 			parent_name);
-	} else {
-		finpll_f = clk_get_rate(clk);
+		finpll_f = 24000000;
 	}
 
 	fclk.id = CLK_FIN_PLL;

drivers/clk/sophgo/clk-sg2042-pll.c

@@ -387,7 +387,7 @@ static int sg2042_clk_pll_set_rate(struct clk_hw *hw,
 	struct sg2042_pll_clock *pll = to_sg2042_pll_clk(hw);
 	struct sg2042_pll_ctrl pctrl_table;
 	unsigned long flags;
-	u32 value;
+	u32 value = 0;
 	int ret;
 
 	spin_lock_irqsave(pll->lock, flags);

drivers/clk/thead/Kconfig

@@ -3,6 +3,7 @@
 config CLK_THEAD_TH1520_AP
 	bool "T-HEAD TH1520 AP clock support"
 	depends on ARCH_THEAD || COMPILE_TEST
+	depends on 64BIT
 	default ARCH_THEAD
 	select REGMAP_MMIO
 	help