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perf/x86/amd: Warn only on new bits set
Warning at every leaking bits can cause a flood of message, triggering various stall-warning mechanisms to fire, including CSD locks, which makes the machine to be unusable. Track the bits that are being leaked, and only warn when a new bit is set. That said, this patch will help with the following issues: 1) It will tell us which bits are being set, so, it is easy to communicate it back to vendor, and to do a root-cause analyzes. 2) It avoid the machine to be unusable, because, worst case scenario, the user gets less than 60 WARNs (one per unhandled bit). Suggested-by: Paul E. McKenney <paulmck@kernel.org> Signed-off-by: Breno Leitao <leitao@debian.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Sandipan Das <sandipan.das@amd.com> Reviewed-by: Paul E. McKenney <paulmck@kernel.org> Link: https://lkml.kernel.org/r/20241001141020.2620361-1-leitao@debian.org
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@ -943,11 +943,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, u
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static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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static atomic64_t status_warned = ATOMIC64_INIT(0);
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u64 reserved, status, mask, new_bits, prev_bits;
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struct perf_sample_data data;
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struct hw_perf_event *hwc;
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struct perf_event *event;
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int handled = 0, idx;
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u64 reserved, status, mask;
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bool pmu_enabled;
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/*
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@ -1012,7 +1013,12 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
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* the corresponding PMCs are expected to be inactive according to the
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* active_mask
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*/
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WARN_ON(status > 0);
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if (status > 0) {
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prev_bits = atomic64_fetch_or(status, &status_warned);
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// A new bit was set for the very first time.
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new_bits = status & ~prev_bits;
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WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits);
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}
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/* Clear overflow and freeze bits */
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amd_pmu_ack_global_status(~status);
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