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Delete regulator-compatible usage in mt8135-evbp1.dts.

Browse Source 
The regualtor-compatible binding is deprecated, instead the node name
 is used.
 
 Mediatek timer driver supports as well mt8127, mt8135 and mt8173. Add
 these SOCs to the bindings list.
 
 Power domains venc and venc_lt need clocks two extra clocks to access
 their registers. We update the bindings documentation about this.
 
 Update SMP bindings documentation by adding support for mt6589 and mt81xx SOCs.
 
 Update mt8127.dtsi and mt8135.dtsi to enable SMP support.
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Merge tag 'v4.3-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt

Delete regulator-compatible usage in mt8135-evbp1.dts.
The regualtor-compatible binding is deprecated, instead the node name
is used.

Mediatek timer driver supports as well mt8127, mt8135 and mt8173. Add
these SOCs to the bindings list.

Power domains venc and venc_lt need clocks two extra clocks to access
their registers. We update the bindings documentation about this.

Update SMP bindings documentation by adding support for mt6589 and mt81xx SOCs.

Update mt8127.dtsi and mt8135.dtsi to enable SMP support.

* tag 'v4.3-next-dts' of https://github.com/mbgg/linux-mediatek:
  ARM: dts: mt8127: enable basic SMP bringup for mt8127
  ARM: dts: mt8135: enable basic SMP bringup for mt8135
  devicetree: bindings: add new SMP enable method Mediatek SoC
  dt-bindings: soc: Add clocks for Mediatek SCPSYS unit
  dt-bindings: add more MediaTek SoC to mtk-timer binding
  ARM: dts: mt8135-evbp1: remove regulator-compatible usage

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2015-10-23 10:24:44 -07:00
commit de0b2a545c
6 changed files with 67 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/cpus.txt
View File

@ -195,6 +195,8 @@ nodes to be present and contain the properties described below.
"marvell,armada-380-smp"
"marvell,armada-390-smp"
"marvell,armada-xp-smp"
"mediatek,mt6589-smp"
"mediatek,mt81xx-tz-smp"
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"

10
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
View File

@ -17,9 +17,9 @@ Required properties:
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
- clock, clock-names: clocks according to the common clock binding.
The clocks needed "mm" and "mfg". These are the
clocks which hardware needs to be enabled before
enabling certain power domains.
The clocks needed "mm", "mfg", "venc" and "venc_lt".
These are the clocks which hardware needs to be enabled
before enabling certain power domains.
Example:
@ -30,7 +30,9 @@ Example:
infracfg = <&infracfg>;
clocks = <&clk26m>,
<&topckgen CLK_TOP_MM_SEL>;
clock-names = "mfg", "mm";
<&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "mfg", "mm", "venc", "venc_lt";
};
Example consumer:

8
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
View File

@ -3,10 +3,12 @@ Mediatek MT6577, MT6572 and MT6589 Timers
Required properties:
- compatible should contain:
* "mediatek,mt6589-timer" for MT6589 compatible timers
* "mediatek,mt6580-timer" for MT6580 compatible timers
* "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580,
MT6577)
* "mediatek,mt6589-timer" for MT6589 compatible timers
* "mediatek,mt8127-timer" for MT8127 compatible timers
* "mediatek,mt8135-timer" for MT8135 compatible timers
* "mediatek,mt8173-timer" for MT8173 compatible timers
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers
- reg: Should contain location and length for timers register.
- clocks: Clocks driving the timer hardware. This list should include two
clocks. The order is system clock and as second clock the RTC clock.

27
arch/arm/boot/dts/mt8127.dtsi
View File

@ -23,6 +23,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "mediatek,mt81xx-tz-smp";
cpu@0 {
device_type = "cpu";
@ -47,6 +48,17 @@
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
trustzone-bootinfo@80002000 {
compatible = "mediatek,trustzone-bootinfo";
reg = <0 0x80002000 0 0x1000>;
};
};
clocks {
#address-cells = <2>;
#size-cells = <2>;
@ -72,6 +84,21 @@
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <13000000>;
arm,cpu-registers-not-fw-configured;
};
soc {
#address-cells = <2>;
#size-cells = <2>;

23
arch/arm/boot/dts/mt8135-evbp1.dts
View File

@ -32,7 +32,6 @@
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
@ -41,7 +40,6 @@
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-compatible = "buck_vpca7";
regulator-name = "vpca7";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
@ -50,7 +48,6 @@
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-compatible = "buck_vsramca15";
regulator-name = "vsramca15";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
@ -59,7 +56,6 @@
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-compatible = "buck_vsramca7";
regulator-name = "vsramca7";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
@ -68,7 +64,6 @@
};
mt6397_vcore_reg: buck_vcore {
regulator-compatible = "buck_vcore";
regulator-name = "vcore";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
@ -77,7 +72,6 @@
};
mt6397_vgpu_reg: buck_vgpu {
regulator-compatible = "buck_vgpu";
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -86,7 +80,6 @@
};
mt6397_vdrm_reg: buck_vdrm {
regulator-compatible = "buck_vdrm";
regulator-name = "vdrm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
@ -95,7 +88,6 @@
};
mt6397_vio18_reg: buck_vio18 {
regulator-compatible = "buck_vio18";
regulator-name = "vio18";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
@ -104,19 +96,16 @@
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-compatible = "ldo_vtcxo";
regulator-name = "vtcxo";
regulator-always-on;
};
mt6397_va28_reg: ldo_va28 {
regulator-compatible = "ldo_va28";
regulator-name = "va28";
regulator-always-on;
};
mt6397_vcama_reg: ldo_vcama {
regulator-compatible = "ldo_vcama";
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
@ -124,18 +113,15 @@
};
mt6397_vio28_reg: ldo_vio28 {
regulator-compatible = "ldo_vio28";
regulator-name = "vio28";
regulator-always-on;
};
mt6397_vusb_reg: ldo_vusb {
regulator-compatible = "ldo_vusb";
regulator-name = "vusb";
};
mt6397_vmc_reg: ldo_vmc {
regulator-compatible = "ldo_vmc";
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@ -143,7 +129,6 @@
};
mt6397_vmch_reg: ldo_vmch {
regulator-compatible = "ldo_vmch";
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@ -151,7 +136,6 @@
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-compatible = "ldo_vemc3v3";
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@ -159,7 +143,6 @@
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-compatible = "ldo_vgp1";
regulator-name = "vcamd";
regulator-min-microvolt = <1220000>;
regulator-max-microvolt = <3300000>;
@ -167,7 +150,6 @@
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-compatible = "ldo_vgp2";
regulator-name = "vcamio";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
@ -175,7 +157,6 @@
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-compatible = "ldo_vgp3";
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@ -183,7 +164,6 @@
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@ -191,7 +171,6 @@
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-compatible = "ldo_vgp5";
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
@ -199,7 +178,6 @@
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-compatible = "ldo_vgp6";
regulator-name = "vgp6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@ -207,7 +185,6 @@
};
mt6397_vibr_reg: ldo_vibr {
regulator-compatible = "ldo_vibr";
regulator-name = "vibr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <3300000>;

27
arch/arm/boot/dts/mt8135.dtsi
View File

@ -46,6 +46,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "mediatek,mt81xx-tz-smp";
cpu0: cpu@0 {
device_type = "cpu";
@ -72,6 +73,17 @@
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
trustzone-bootinfo@80002000 {
compatible = "mediatek,trustzone-bootinfo";
reg = <0 0x80002000 0 0x1000>;
};
};
clocks {
#address-cells = <2>;
#size-cells = <2>;
@ -97,6 +109,21 @@
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <13000000>;
arm,cpu-registers-not-fw-configured;
};
soc {
#address-cells = <2>;
#size-cells = <2>;