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ASoC: codecs: lpass: do not reset soundwire block on clk enable
resetting soundwire block will put the slaves out of sync and result in re-enumeration during fsgen disable/enable path this is totally unnecessary and resulting fifo overflows. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20230209122806.18923-8-srinivas.kandagatla@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
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e762143437
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ddffe3b828
@ -3441,16 +3441,10 @@ static int swclk_gate_enable(struct clk_hw *hw)
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}
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}
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rx_macro_mclk_enable(rx, true);
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rx_macro_mclk_enable(rx, true);
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regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_RX_SWR_RESET_MASK,
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CDC_RX_SWR_RESET);
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regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
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regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_RX_SWR_CLK_EN_MASK, 1);
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CDC_RX_SWR_CLK_EN_MASK, 1);
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regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_RX_SWR_RESET_MASK, 0);
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return 0;
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return 0;
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}
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}
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@ -3601,6 +3595,17 @@ static int rx_macro_probe(struct platform_device *pdev)
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if (ret)
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if (ret)
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goto err_fsgen;
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goto err_fsgen;
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/* reset swr block */
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regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_RX_SWR_RESET_MASK,
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CDC_RX_SWR_RESET);
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regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_RX_SWR_CLK_EN_MASK, 1);
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regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_RX_SWR_RESET_MASK, 0);
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ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
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ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
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rx_macro_dai,
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rx_macro_dai,
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ARRAY_SIZE(rx_macro_dai));
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ARRAY_SIZE(rx_macro_dai));
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@ -1861,15 +1861,10 @@ static int swclk_gate_enable(struct clk_hw *hw)
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}
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}
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tx_macro_mclk_enable(tx, true);
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tx_macro_mclk_enable(tx, true);
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regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
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regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
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regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_TX_SWR_CLK_EN_MASK,
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CDC_TX_SWR_CLK_EN_MASK,
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CDC_TX_SWR_CLK_ENABLE);
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CDC_TX_SWR_CLK_ENABLE);
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regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_TX_SWR_RESET_MASK, 0x0);
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return 0;
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return 0;
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}
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}
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@ -2036,6 +2031,16 @@ static int tx_macro_probe(struct platform_device *pdev)
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if (ret)
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if (ret)
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goto err_fsgen;
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goto err_fsgen;
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/* reset soundwire block */
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regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
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regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_TX_SWR_CLK_EN_MASK,
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CDC_TX_SWR_CLK_ENABLE);
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regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
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CDC_TX_SWR_RESET_MASK, 0x0);
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ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
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ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
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tx_macro_dai,
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tx_macro_dai,
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ARRAY_SIZE(tx_macro_dai));
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ARRAY_SIZE(tx_macro_dai));
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@ -1333,17 +1333,9 @@ static int fsgen_gate_enable(struct clk_hw *hw)
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int ret;
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int ret;
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ret = va_macro_mclk_enable(va, true);
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ret = va_macro_mclk_enable(va, true);
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if (!va->has_swr_master)
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if (va->has_swr_master)
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return ret;
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regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
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regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_VA_SWR_RESET_MASK, CDC_VA_SWR_RESET_ENABLE);
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CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE);
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regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_VA_SWR_CLK_EN_MASK,
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CDC_VA_SWR_CLK_ENABLE);
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regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_VA_SWR_RESET_MASK, 0x0);
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return ret;
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return ret;
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}
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}
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@ -1538,6 +1530,15 @@ static int va_macro_probe(struct platform_device *pdev)
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}
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}
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if (va->has_swr_master) {
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regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_VA_SWR_RESET_MASK, CDC_VA_SWR_RESET_ENABLE);
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regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE);
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regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_VA_SWR_RESET_MASK, 0x0);
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}
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ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
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ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
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va_macro_dais,
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va_macro_dais,
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ARRAY_SIZE(va_macro_dais));
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ARRAY_SIZE(va_macro_dais));
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@ -2270,17 +2270,10 @@ static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
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}
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}
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wsa_macro_mclk_enable(wsa, true);
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wsa_macro_mclk_enable(wsa, true);
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/* reset swr ip */
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regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_ENABLE);
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regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_WSA_SWR_CLK_EN_MASK,
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CDC_WSA_SWR_CLK_EN_MASK,
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CDC_WSA_SWR_CLK_ENABLE);
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CDC_WSA_SWR_CLK_ENABLE);
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/* Bring out of reset */
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regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_DISABLE);
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} else {
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} else {
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regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_WSA_SWR_CLK_EN_MASK, 0);
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CDC_WSA_SWR_CLK_EN_MASK, 0);
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@ -2451,6 +2444,17 @@ static int wsa_macro_probe(struct platform_device *pdev)
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if (ret)
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if (ret)
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goto err_fsgen;
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goto err_fsgen;
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/* reset swr ip */
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regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_ENABLE);
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regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_WSA_SWR_CLK_EN_MASK, CDC_WSA_SWR_CLK_ENABLE);
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/* Bring out of reset */
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regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
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CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_DISABLE);
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ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
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ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
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wsa_macro_dai,
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wsa_macro_dai,
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ARRAY_SIZE(wsa_macro_dai));
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ARRAY_SIZE(wsa_macro_dai));
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